Power reduction technique during write bursts

A system, comprising:

• a processor;
• one or more memory devices coupled to the processor, each comprising:
• a memory bank comprising memory storage circuitry;
• a data sense amplifier write driver;
• voltage regulation circuitry configured to supply a voltage signal between a HIGH signal and a LOW signal;
• a first data line coupled to the data sense amplifier write driver, wherein the first data line is configured to provide a first charge to the voltage regulation circuitry during a first mode of operation, wherein the voltage regulation circuitry is configured to generate the voltage signal based on the first charge;
• and
• a second data line coupled to the data sense amplifier write driver, wherein the second data line is configured to draw a second charge from the voltage signal supplied from the voltage regulation circuitry to control the voltage on the second data line during a second mode of operation.

A method, comprising:

• charging a first data line of a memory bank to be in a HIGH state;
• during a read operation, providing a first charge from the first data line to voltage regulation circuitry to store the first charge from the first data line at the voltage regulation circuitry and to control a value read from the memory bank;
• and
• during a write operation, providing a second charge to a second data line of the memory bank based at least in part on the first charge stored at the voltage regulation circuitry to control the value stored during the write operation.