Memory device and operating method thereof

A method for operating a memory device including a plurality of word lines, a plurality of bit lines and a plurality of memory cells, each memory cell coupled to a corresponding word line among the plurality of word lines and a corresponding bit line among the plurality of bit lines, the method comprising:

• activating at least two word lines together among the plurality of word lines;
• sharing charges between memory cells coupled to the same bit line among memory cells coupled to the activated word lines and the bit line;
• and
• determining that a weak cell exists among the memory cells coupled to the activated word lines, based on a voltage of the bit line corresponding to the activated word lines being lower than a reference voltage, and determining that the weak cell does not exist among the memory cells coupled to the activated word lines, when the voltage of the bit line corresponding to the activated word lines is equal to or higher than the reference voltage.

A memory device comprising:

• first to nth (where n is a natural number) word line groups each including at least two word lines;
• and
• a control block suitable for controlling the first to nth word line groups to be activated sequentially, and determining whether or not a weak cell exists among memory cells coupled to an activated word line group, based on a voltage of a bit line corresponding to the activated word line group,
• wherein the control block determines that the weak cell exists among the memory cells coupled to the activated word line group, when the voltage of the bit line corresponding to the activated word line group is lower than a reference voltage, and determines that the weak cell does not exist among the memory cells coupled to the activated word line group, when the voltage of the bit line corresponding to the activated word line group is equal to or higher than the reference voltage.