Back to results
US 10,255,964 B2Granted
Semiconductor memory device having clock generation scheme based on command
AssigneeSamsung Electronics Co., Ltd.
InventorsSeungjun Shin, Su Yeon Doo, Taeyoung Oh
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a command decoder configured to generate an auto-sync signal in response to a command for writing data at a memory cell or reading data from a memory cell, and an internal data clock generating circuit configured to phase synchronize a second clock, having a clock frequency higher than a clock frequency of a first clock, with the first clock in response to the auto-sync signal.
Claims17
A semiconductor memory device comprising:
- a command decoder configured to generate an auto-sync signal in response to a command for writing data to a memory cell or reading data from a memory cell;
- an internal data clock generating circuit configured to adjust a phase of a second clock to be synchronized with a phase of a first clock in response to the auto-sync signal, wherein a frequency of the second clock is higher than a frequency of the first clock,
- wherein the first clock is a system clock associated with a transfer rate of the command or an address, and the second clock is a data clock associated with an input/output rate of the data;
- and
- a pattern generator configured to generate a detection clock pattern in response to the command.
2 more elements
A semiconductor memory device comprising:
- a command decoder configured to generate an auto-sync signal in response to a command for writing data to a memory cell or reading data from a memory cell;
- and
- an internal data clock generating circuit configured to adjust a phase of a second clock to be synchronized with a phase of a first clock in response to the auto-sync signal, wherein a frequency of the second clock is higher than a frequency of the first clock,
- wherein the auto-sync signal is a pulse signal which is delayed by a predetermined time from an end point of an input command, and
- wherein the second clock starts to toggle before the command is received.
2 more elements
A semiconductor memory device comprising:
- a decoder configured to generate a mode selection signal in response to a command;
- and
- a dual clock managing circuit configured to selectively activate one of a first mode clock generator and a second mode clock generator in response to the mode selection signal,
- wherein the first mode clock generator uses a first system clock having a first clock frequency and a data clock having a clock frequency higher than the first system clock,
- wherein the second mode clock generator uses a second system clock having a second clock frequency higher than the first clock frequency and a data output strobe signal of which a frequency is the same as the second clock frequency, and
- wherein an activating frequency of the first mode clock generator is higher than an activating frequency of the second mode clock generator.
3 more elements
Dependencies are inferred from the claim text.