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US 10,255,963 B2Granted
Apparatus having dice to perform refresh operations
AssigneeMicron Technology, Inc.
InventorTaihei Shido
Life of this patent
Estimating the term…
Abstract
Some embodiments include an apparatus that comprise an interface chip having an oscillator to produce an original clock signal, a first memory chip having first memory cells, and a second memory chip having second memory cells. The first memory cells may be refreshed in response to a first clock signal based on the original clock signal. The second memory cells may be refreshed in response to a second clock signal based on the original clock signal.
Claims15
An apparatus comprising:
- a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip;
- and
- an interface chip coupled to the chip stack structure,
- wherein the interface chip is configured to transfer a first input clock signal based on an original clock signal to the first memory chip, and a second input clock signal based on the original clock signal to the second memory chip, and to independently transfer a first command signal to the first memory chip and a second command signal to the second memory chip, and wherein the interface chip further comprises an oscillator configured to produce the original clock signal.
1 more element
An apparatus comprising:
- a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip;
- and
- an interface chip coupled to the chip stack structure,
- wherein the interface chip is configured to transfer a clock signal to both of the first memory chip and the second memory chip, and to independently transfer a first command signal to the first memory chip and a second command signal to the second memory chip,
- wherein the interface chip comprises a first terminal supplied with the first command signal and a second terminal supplied with the second command signal;
- wherein the first memory chip comprises a third terminal coupled to the first terminal and a fourth terminal coupled to the second terminal;
- and
- wherein the second memory chip comprises a fifth terminal coupled to the second terminal by way of the fourth terminal.
5 more elements
An apparatus comprising:
- a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip;
- and
- an interface chip coupled to the chip stack structure,
- wherein the first memory chip comprises a first command decoder circuit, a first terminal to receive a first clock signal, a second terminal coupled to the first command decoder circuit, and a plurality of first memory cells,
- wherein the second memory chip comprises a second command decoder circuit, a third terminal to receive a second clock signal, a fourth terminal coupled to the second command decoder circuit, a fifth terminal, and a plurality of second memory cells,
- wherein the second terminal of the first memory chip is electrically pled to the fifth terminal of the second memory chip, and
- wherein the interface chip comprises sixth, seventh, and eighth terminals respectively electrically coupled to the third, fourth and fifth terminals of the second memory chips.
4 more elements
An apparatus, comprising:
- a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip;
- an interface chip coupled to the chip stack structure, wherein the interface chip is configured to generate a clock signal and to transfer the clock signal to both of the first memory chip and the second memory chip, and to independently transfer a first command signal to the first memory chip to facilitate a first data refresh operation on the first memory chip, and a second command signal to the second memory chip to facilitate a second data refresh operation on the second memory chip;
- a first delay circuit introducing a first delay of the clock signal utilized for the first refresh operation on the first memory chip relative to the clock signal generated on the interface chip;
- and
- a second delay circuit introducing a second delay of the clock signal utilized for the second refresh operation on the second memory chip relative to the clock signal generated on the interface chip, wherein each of the first and second delay circuits is located on the interface chip.
2 more elements
A method, comprising:
- generating an original clock signal on an interface chip through use of an oscillator on the interface chip, wherein the interface chip is coupled to a chip stack structure comprising a first memory chip and a second memory chip stacked over the first memory chip;
- activating the oscillator in response to a reset signal received by the interface chip;
- establishing a first clock signal for use by the first memory chip, the first clock signal based on the original clock signal;
- establishing a second clock signal for use by the second memory chip, the second clock signal based on the original clock signal;
- transferring a first command signal from the interface chip to the first memory chip to facilitate performing a first data refresh operation on the first memory chip through use of the first clock signal;
- and
- transferring a second command signal from the interface chip to the second memory chip to facilitate performing of a second data refresh operation on the second memory chip through use of the second clock signal.
4 more elements
Dependencies are inferred from the claim text.