Write pulse generator in a resistive memory
AssigneeToshiba Memory Corporation
InventorNaoki Shimizu
Life of this patent
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Abstract
According to one embodiment, a semiconductor memory device comprises a memory cell including a variable resistance element; and a first circuit configured to control writing to the memory cell. The first circuit is configured to generate a first pulse of a second signal based on a first signal from outside, generate a second pulse of a third signal obtained by delaying the first pulse, and generate a third pulse of a fourth signal obtained by delaying the second pulse. A falling edge of the first pulse is based on a rising edge of the second pulse. A write pulse is output based on the fourth signal.
Claims17
A semiconductor memory device comprising:
- a memory cell including a variable resistance element;
- and
- a first circuit configured to control writing to the memory cell,
- wherein the first circuit is configured to generate a first pulse of a second signal based on a first signal, generate a second pulse of a third signal obtained by delaying the first pulse, and generate a third pulse of a fourth signal obtained by delaying the second pulse,
- wherein the first circuit includes:
- a counter configured to count a number of third pulses of the fourth signal;
- and
- a multiplexer configured to output either the first signal or the fourth signal as the first signal based on the number of third pulses counted by the counter, and
- wherein the first circuit outputs a write pulse based on the fourth signal.
A semiconductor memory device comprising:
- a memory cell including a variable resistance element;
- and
- a first circuit configured to control writing to the memory cell,
- wherein the first circuit includes:
- a second circuit configured to output a second signal based on a first signal;
- a third circuit configured to output a third signal obtained by delaying the second signal;
- a fourth circuit configured to output a fourth signal obtained by delaying the third signal;
- a fifth circuit configured to count a number of third pulses of the fourth signal;
- and
- a sixth circuit configured to output either the first signal or the fourth signal to the second circuit as the first signal based on the number of third pulses counted by the fifth circuit, and
- wherein the first circuit outputs a write pulse based on the fourth signal.
Dependencies are inferred from the claim text.