Memory devices configured to prevent read failure due to leakage current into bit line

A memory device comprising:

• a memory cell array including a selected memory cell connected to a selected bit line, a reference cell connected to a reference bit line, and a sub cell connected to a sub bit line;
• and
• a sense amplifier configured to sense a voltage difference between a first node through which a first current is input to the reference bit line and a second node through which a second current is input to the reference bit line and the sub bit line,
• wherein the sub cell includes:
• a magnetic tunnel junction element, a first end of which is connected to the sub bit line;
• and
• a cell transistor having a first end connected to a second end of the magnetic tunnel junction element, a second end connected to a sub source line, and a gate electrode connected to the sub source line.

A memory device comprising:

• a memory cell array including a selected memory cell connected to a selected bit line, a reference cell connected to a reference bit line, a first sub cell connected to a first sub bit line, and a second sub cell connected to a second sub bit line;
• a sense amplifier configured to sense a voltage difference between a first node through which a first current is input to the reference bit line and a second node through which a second current is input to the reference bit line, the first sub bit line, and the second sub bit line;
• and
• control logic configured to selectively connect the first sub bit line and the second sub bit line to the second node.