Semiconductor devices and semiconductor systems including the same

A semiconductor device comprising:

• a first command generation circuit configured to generate a first normal command if a first internal chip selection signal having an enabled state is inputted to the first command generation circuit in synchronization with an inverted internal clock signal while a first internal control signal having a first predetermined state is inputted to the first command generation circuit in synchronization with an internal clock signal, and configured to generate a first control command if the first internal control signal having a second predetermined state is inputted to the first command generation circuit in synchronization with the inverted internal clock signal while the first internal control signal having the first predetermined state is inputted to the first command generation circuit in synchronization with the internal clock signal;
• and
• a second command generation circuit configured to generate a second normal command if a second internal chip selection signal having an enabled state is inputted to the second command generation circuit in synchronization with the internal clock signal while a second internal control signal having a third predetermined state is inputted to the second command generation circuit in synchronization with the inverted internal clock signal, and configured to generate a second control command if the second internal control signal having a fourth predetermined state is inputted to the second command generation circuit in synchronization with the internal clock signal while the second internal control signal having the third predetermined state is inputted to the second command generation circuit in synchronization with the inverted internal clock signal.

A semiconductor system comprising:

• a semiconductor controller configured to generate an external control signal, an external chip selection signal and an external clock signal;
• and
• a semiconductor module configured to receive the external control signal, the external chip selection signal, and the external clock signal to communicate data with the semiconductor controller,
• wherein the semiconductor module includes:
• a register clock driver configured to generate a control signal, a chip selection signal, and a clock signal from the external control signal, the external chip selection signal, and the external clock signal;
• and
• a first command generation circuit configured to generate a first normal command and a first control command in response to the control signal, the chip selection signal and the clock signal,
• wherein the first normal command is generated if a first internal chip selection signal having an enabled state is inputted to the first command generation circuit in synchronization with an inverted internal clock signal while a first internal control signal having a first predetermined state is inputted to the first command generation circuit in synchronization with an internal clock signal, and
• wherein the first control command is generated if the first internal control signal having a second predetermined state is inputted to the first command generation circuit in synchronization with the inverted internal clock signal while the first internal control signal having the first predetermined state is inputted to the first command generation circuit in synchronization with the internal clock signal.