Gate driving circuit, array substrate, display panel and driving method thereof

A gate driving circuit, comprising:

• n stages that are sequentially arranged, n being an integer larger than or equal to 4, wherein the n stages are divided into a first set of stages comprising a (4k+1)-th stage of the n stages, a second set of stages comprising a (4k+2)-th stage of the n stages, a third set of stages comprising a (4k+3)-th stage of the n stages, and a fourth set of stages comprising a 4(k+1)-th stage of the n stages, k being an integer larger than or equal to 0, and wherein the first, second, third and fourth sets of stages are configured to receive respective different combinations of a first clock signal, a second clock signal, a third clock signal and a fourth clock signal,
• a first clock line for transmitting the first clock signal,
• a second clock line for transmitting the second clock signal,
• a third clock line for transmitting the third clock signal,
• a fourth clock line for transmitting the fourth clock signal,
• a first scan start signal line for transmitting the first scan start signal, and
• a second scan start signal line for transmitting the second scan start signal,
• wherein the stages in the first set of stages and the stages in the third set of stages are cascaded with each other, and the stages in the second set of stages and the stages in the fourth set of stages are cascaded with each other,
• wherein first two of the n stages are configured to receive a first scan start signal and last two of the n stages are configured to receive a second scan start signal,
• wherein each of the n stages comprises a first clock terminal, a second clock terminal, a third clock terminal and a fourth clock terminal,
• wherein the first clock line is connected to the third clock terminal of each stage in the first set of stages, the second clock terminal of each stage in the second set of stages, the first clock terminal of each stage in the third set of stages, and the fourth clock terminal of each stage in the fourth set of stages,
• wherein the second clock line is connected to the fourth clock terminal of each stage in the first set of stages, the third clock terminal of each stage in the second set of stages, the second clock terminal of each stage in the third set of stages, and the first clock terminal of each stage in the fourth set of stages,
• wherein the third clock line is connected to the first clock terminal of each stage in the first set of stages, the fourth clock terminal of each stage in the second set of stages, the third clock terminal of each stage in the third set of stages, and the second clock terminal of each stage in the fourth set of stages,
• wherein the fourth clock line is connected to the second clock terminal of each stage in the first set of stages, the first clock terminal of each stage in the second set of stages, the fourth clock terminal of each stage in the third set of stages, and the third clock terminal of each stage in the fourth set of stages,
• wherein each of the n stages further comprises an input terminal, an output terminal, a reset terminal, and a gate-off voltage terminal configured to receive a gate-off voltage,
• wherein the output terminal of each stage in the first set of stages is connected to the input terminal of a respective next stage in the third set of stages, and the output terminal of each stage in the third set of stages is connected to the reset terminal of a respective previous stage in the first set of stages and the input terminal of a respective next stage in the first set of stages,
• wherein the output terminal of each stage in the second set of stages is connected to the input terminal of a respective next stage in the fourth set of stages, and the output terminal of each stage in the fourth set of stages is connected to the reset terminal of a respective previous stage in the second set of stages and the input terminal of a respective next stage in the second set of stages, and
• wherein the input terminals of the first two of the n stages are connected to the first scan start signal line, and the reset terminals of the last two of the n stages are connected to the second scan start signal line.