Scan driver and display device including the same

A scan driver comprising a plurality of stages, wherein each stage outputs a scan signal in response to receiving a scan start pulse and a plurality of clock signals, and each stage comprises:

• a first transistor comprising a gate that receives the scan start pulse, or the scan signal from a previous stage, and further comprising a first terminal coupled to a high gate voltage, and a second terminal coupled to a first node;
• a second transistor comprising a gate coupled to the first node, a first terminal that receives a first one of the plurality of clock signals, and a second terminal coupled to a second node;
• a third transistor comprising a gate coupled to the first node, a first terminal that receives a second one of the plurality of clock signals, and a second terminal coupled to an output node;
• a first capacitor comprising a first electrode coupled to the first node, and a second electrode coupled to the output node;
• a fourth transistor comprising a gate coupled to the second node, a first terminal coupled to the output node, and a second terminal coupled to a low gate voltage;
• a second capacitor comprising a first electrode coupled to the second node, and a second electrode coupled to the low gate voltage;
• a fifth transistor coupled between the first node and the output node;
• a sixth transistor comprising a gate that receives the second one of the plurality of clock signals, and a second terminal;
• a seventh transistor comprising a gate coupled to the second node, a first terminal coupled to the second terminal of the sixth transistor, and a second terminal coupled to the output node;
• an eighth transistor comprising a gate that receives the first one of the plurality of clock signals, a first terminal coupled to the second node, and a second terminal coupled to the high gate voltage;
• and
• a ninth transistor comprising a gate coupled to the second node, a first terminal coupled to the second node, and a second terminal coupled to the high gate voltage.

A display device, comprising:

• a display panel comprising a plurality of pixels;
• a data driver configured to provide a data signal to the pixels;
• a scan driver comprising a plurality of stages, wherein each stage provides a scan signal to the pixels in response to receiving a scan start pulse and a plurality of clock signals;
• and
• a timing controller configured to control the data driver and the scan driver,
• wherein each stage of the scan driver comprises:
• a first input circuit configured to apply a high gate voltage to a first node in response to receiving the scan start pulse, or the scan signal from a previous stage;
• a second input circuit configured to apply a first one of the plurality of clock signals to a second node in response to a voltage of the first node;
• a first output circuit configured to output a second one of the plurality of clock signals as the scan signal in response to the voltage of the first node;
• a second output circuit configured to output a low gate voltage as the scan signal in response to a voltage of the second node;
• and
• a leakage circuit coupled to the high gate voltage, and configured to provide a current from the high gate voltage to the second node in response to the voltage of the second node having a high level,
• wherein the leakage circuit comprises a transistor comprising agate coupled to the second node, a first terminal coupled to the second node and a second terminal coupled to the high gate voltage.