Gate driver and a display apparatus including the same

A display apparatus comprising:

• a display panel including a plurality of gate lines, a plurality of data lines, and a plurality of pixels connected to the plurality of gate lines and the plurality of data lines;
• a data driver configured to generate a plurality of data voltages applied to the plurality of data lines;
• and
• a gate driver configured to generate a plurality of gate signals applied to the plurality of gate lines, wherein the gate driver includes a plurality of cascaded stages,
• wherein an N-th stage (where N is a natural number) among the plurality of stages comprises:
• a first control circuit configured to control a first signal at a first node in response to a first input signal;
• a gate signal generating circuit configured to generate an N-th gate signal among the plurality of gate signals at a second node in response to a clock signal and the first signal;
• a carry signal generating circuit configured to generate an N-th carry signal among a plurality of carry signals at a third node in response to the clock signal and the first signal;
• a second control circuit configured to control the first signal in response to a second input signal;
• a third control circuit configured to generate a hold control signal at a fourth node in response to a third input signal having a frequency lower than that of the clock signal;
• and
• a holding circuit configured to maintain a level of the first signal, a level of the N-th gate signal, and a level of the N-th carry signal in response to the hold control signal,
• wherein the first input signal is an (N−1)-th carry signal, among the plurality of carry signals, generated from an (N−1)-th stage among the plurality of stages,
• wherein the second input signal is an (N+2)-th carry signal, among the plurality of carry signals, generated from an (N+2)-th stage among the plurality of stages,
• wherein, in a first stage among the plurality of stages, the first input signal is a vertical start signal and not the (N−1)-th carry signal, and
• wherein, in a last stage and a penultimate stage among the plurality of stages, the second input signal is the vertical start signal and not the (N+2)-th carry signal.