Scan driving circuit and flat display device thereof
AssigneeWuhan China Star Optoelectronics Technology Co., Ltd.
InventorsGuanghui Hong, Qiang Gong, Chunqian Zhang
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Abstract
The disclosure discloses a flat panel display device and a scan driving circuit thereof. The scan driving circuit includes a plurality of first scan drivers and a plurality of second scan drivers that are cascaded, the plurality of first scan drivers and the plurality of second scan drivers receive a clock signal alternately. The plurality of first scan drivers and the plurality of second scan drivers perform cascaded transmission according to the clock signal. The disclosure performs cascaded transmission by interposing a clock signal, which can reduce the amount of input signals and simplify the array process.
Claims12
A scan driving circuit, the scan driving circuit comprising a plurality of first scan drivers and a plurality of second scan drivers that are cascaded, wherein the plurality of first scan drivers and the plurality of second scan drivers receive a clock signal alternately, and the plurality of first scan drivers and the plurality of second scan drivers perform cascaded transmission according to the clock signal,
- wherein each of the first scan drivers comprises:
- a first latch circuit configured to receive the clock signal and a driving signal and output a first input signal;
- a first output circuit configured to receive the first input signal, the driving signal, a first control signal and a second control signal, output a first scanning signal according to the first control signal and output a second scanning signal according to the second control signal;
- and
- a first reset circuit configured to receive a first voltage reference and a first reset signal, and configured to reset the first scan drivers,
- wherein the first latch circuit comprises a first inverter, a first clock inverter and a second clock inverter, a first terminal of the first inverter, a fourth terminal of the first clock inverter and a second terminal of the second clock inverter receive the clock signal, a second terminal of the first inverter is connected with a second terminal of the first clock inverter and a fourth terminal of the second clock inverter, a first terminal of the first clock inverter receives the driving signal, a third terminal of the first clock inverter is connected with a third terminal of the second clock inverter, and a first terminal of the second clock inverter outputs the first input terminal,
- wherein the first output circuit comprises a first NAND gate, a second NAND gate, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter, wherein a first terminal of the first NAND gate receives the first control signal, a second terminal of the first NAND gate and a second terminal of the second NAND gate are connected with a first terminal of the second clock inverter, a third terminal of the first NAND gate and a third terminal of the second NAND gate receive the driving signal, an output terminal of the first NAND gate is connected with an input terminal of the second inverter, an output terminal of the second inverter is connected with an input terminal of the third inverter, an output terminal of the third inverter is connected with an input terminal of the fourth inverter, and an output terminal of the fourth inverter outputs the first scanning signal, and
- wherein a first terminal of the second NAND gate receives the second control signal, an output terminal of the second NAND gate is connected with an input terminal of the fifth inverter, an output terminal of the fifth inverter is connected with an input terminal of the sixth inverter, an output terminal of the sixth inverter is connected with an input terminal of the seventh inverter, and an output terminal of the seventh inverter outputs the second scanning signal.
A flat display device, the flat display device comprising a scan driving circuit, wherein the scan driving circuit comprises a plurality of first scan drivers and a plurality of second scan drivers that are cascaded, the plurality of first scan drivers and the plurality of second scan drivers receive a clock signal alternately, and the plurality of first scan drivers and the plurality of second scan drivers perform cascaded transmission according to the clock signal,
- wherein each of the first scan drivers comprises:
- a first latch circuit configured to receive the clock signal and a driving signal and output a first input signal;
- a first output circuit configured to receive the first input signal, the driving signal, a first control signal and a second control signal, output a first scanning signal according to the first control signal and output a second scanning signal according to the second control signal;
- and
- a first reset circuit configured to receive a first voltage reference and a first reset signal, configured to reset the first scan drivers,
- wherein the first latch circuit comprises a first inverter, a first clock inverter and a second clock inverter, a first terminal of the first inverter, a fourth terminal of the first clock inverter and a second terminal of the second clock inverter receive the clock signal, a second terminal of the first inverter is connected with a second terminal of the first clock inverter and a fourth terminal of the second clock inverter, a first terminal of the first clock inverter receives the driving signal, a third terminal of the first clock inverter is connected with a third terminal of the second clock inverter, and a first terminal of the second clock inverter outputs the first input terminal,
- wherein the first output circuit comprises a first NAND gate, a second NAND gate, a second inverter, a third inverter, a fourth inverter, a fifth inverter, a sixth inverter and a seventh inverter, wherein a first terminal of the first NAND gate receives the first control signal, a second terminal of the first NAND gate and a second terminal of the second NAND gate are connected with a first terminal of the second clock inverter, a third terminal of the first NAND gate and a third terminal of the second NAND gate receive the driving signal, an output terminal of the first NAND gate is connected with an input terminal of the second inverter, an output terminal of the second inverter is connected with an input terminal of the third inverter, an output terminal of the third inverter is connected with an input terminal of the fourth inverter, and an output terminal of the fourth inverter outputs the first scanning signal, and
- wherein a first terminal of the second NAND gate receives the second control signal, an output terminal of the second NAND gate is connected with an input terminal of the fifth inverter, an output terminal of the fifth inverter is connected with an input terminal of the sixth inverter, an output terminal of the sixth inverter is connected with an input terminal of the seventh inverter, and an output terminal of the seventh inverter outputs the second scanning signal.
Dependencies are inferred from the claim text.