Processor power supply glitch mitigation
AssigneeSqaure, Inc.
InventorsAfshin Rezayee, Malcolm Ronald Smith, Yue Yang
Life of this patent
Estimating the term…
Abstract
A transaction device includes a bootloader that a processing unit executes during device startup. The bootloader causes the processing unit to access values from a persistent memory that are relevant to whether a glitch has occurred on a power supply for the processing unit. Based on the values that are acquired from the persistent memory, the processing unit may implement countermeasures, such as disabling certain device operations or delaying the device booting process.
Claims35
A payment reader configured to detect and mitigate the occurrence of glitches during execution of bootloader instructions of the payment reader, comprising:
- at least one bootloader memory, the bootloader memory comprising glitch instructions and bootloader instructions;
- at least one battery-backed memory, the battery-backed memory comprising storage for an exception count, an exception limit, and a delay value;
- at least one processing unit, wherein the at least one processing unit executes the glitch instructions on a startup of the payment reader, and wherein the glitch instructions cause the at least one processing unit to:
- access the exception count and the exception limit from the battery-backed memory, determine whether the exception count exceeds the exception limit,
- disable a cryptographic key when the exception count exceeds the exception limit, identify, when the exception count does not exceed the exception limit, a delay based on the exception count and the delay value, and
- execute, after the delay, the bootloader instructions, wherein the processor is configured to identify an exception during execution of the bootloader instructions, and to increment the exception count when the exception is identified.
A transaction device including power supply glitch mitigation, the transaction device comprising:
- at least one bootloader memory, the bootloader memory comprising glitch instructions and bootloader instructions;
- at least one persistent memory, the persistent memory comprising storage for one or more glitch values;
- at least one processing unit, wherein the at least one processing unit executes the glitch instructions prior to executing the bootloader instructions, and wherein the glitch instructions cause the at least one processing unit to:
- access the one or more glitch values from the persistent memory,
- determine whether the one or more glitch values satisfy a first glitch criteria;
- disable one or more operations of the transaction device when the one or more glitch values satisfy the first glitch criteria;
- determine whether the one or more glitch values satisfy a second glitch criteria;
- identify a delay when the glitch values satisfy the second glitch criteria;
- and
- execute, after the delay, the bootloader instructions.
A method for mitigating power supply glitches at a transaction device, the method comprising:
- accessing, by a processing unit of the transaction device, one or more glitch values from a persistent memory;
- determining, by the processing unit, whether the one or more glitch values satisfy a first glitch criteria;
- disabling, by the processing unit, one or more operations of the transaction device when the one or more glitch values satisfy the first glitch criteria;
- determining, by the processing unit, whether the one or more glitch values satisfy a second glitch criteria;
- identifying, by the processing unit, a delay when the glitch values satisfy the second glitch criteria;
- and
- executing, after the delay, bootloader instructions.
A non-transitory computer-readable storage medium comprising glitch instructions stored therein, which when executed by one or more processors of a transaction device, cause the one or more processors to perform operations comprising:
- accessing one or more glitch values from a persistent memory;
- determining whether the one or more glitch values satisfy a first glitch criteria;
- disabling one or more operations of the transaction device when the one or more glitch values satisfy the first glitch criteria;
- determining whether the one or more glitch values satisfy a second glitch criteria;
- identifying a delay when the glitch values satisfy the second glitch criteria;
- and
- initiating execution of bootloader instructions after the delay.
Dependencies are inferred from the claim text.