Apparatus and method for obfuscating power consumption of a processor

An apparatus for obfuscating a first power consumption associated with one or more operations of a logic circuitry of a processor, the apparatus comprising:

• counterbalance circuitry configured to provide a second power consumption to directly counterbalance the first power consumption associated with the one or more operations of the logic circuitry, wherein the second power consumption varies inversely with the first power consumption associated with the one or more operations of the logic circuitry;
• and
• header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry;
• wherein the counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node,
• wherein the counterbalance circuitry comprises:
• a second PMOS transistor connected between a first reference voltage supply and a first node;
• a third PMOS transistor connected between the first node and a second reference voltage supply;
• and
• a fourth PMOS transistor connected between the first reference voltage supply and the second reference voltage supply;
• wherein a gate of the second PMOS transistor is connected to the logic circuitry at the common node, a gate of the third PMOS transistor is configured to receive a selection signal, and a gate of the fourth PMOS transistor is connected to the first node.

An apparatus for obfuscating a first power consumption associated with one or more operations of a logic circuitry of a processor, the apparatus comprising:

• counterbalance circuitry configured to provide a second power consumption to directly counterbalance the first power consumption associated with the one or more operations of the logic circuitry, wherein the second power consumption varies inversely with the first power consumption associated with the one or more operations of the logic circuitry;
• and
• header circuitry configured to enable a common node to vary in voltage corresponding to the one or more operations of the logic circuitry;
• wherein the counterbalance circuitry and the header circuitry are each coupled to the logic circuitry at the common node, wherein the counterbalance circuitry comprises:
• a second PMOS transistor connected between a first reference voltage supply and a first node;
• a fourth PMOS transistor connected between the first reference voltage supply and a second reference voltage supply;
• and
• a plurality of PMOS transistors connected in parallel between the first node and the second reference voltage;
• wherein a gate of the second PMOS transistor is connected to the logic circuitry at the common node and a gate of the fourth PMOS transistor is connected to the first node, and wherein a plurality of second selection signals control the plurality of PMOS transistors.

An apparatus for obfuscating a first power consumption associated with one or more operations of a logic circuitry of a processor, the apparatus comprising:

• counterbalance circuitry configured to provide a second power consumption to predictively counterbalance the first power consumption associated with the one or more operations of the logic circuitry, wherein the second power consumption varies inversely with the first power consumption associated with the one or more operations of the logic circuitry;
• and
• header circuitry configured to enable the one or more operations of the logic circuitry, wherein the header circuitry and the counterbalance circuitry are configured to receive a selection signal,
• wherein the counterbalance circuitry comprises a second PMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, and wherein the second PMOS transistor, the third PMOS transistor, and the fourth PMOS transistor are sized based on estimates of the first power consumption.

An apparatus for obfuscating a first power consumption associated with one or more operations of a logic circuitry of a processor, the apparatus comprising:

• counterbalance circuitry configured to provide a second power consumption to predictively counterbalance the first power consumption associated with the one or more operations of the logic circuitry, wherein the second power consumption varies inversely with the first power consumption associated with the one or more operations of the logic circuitry;
• and
• header circuitry configured to enable the one or more operations of the logic circuitry, wherein the header circuitry and the counterbalance circuitry are configured to receive a selection signal,
• wherein the counterbalance circuitry comprises a plurality of sub-counterbalance circuits connected in parallel between a first reference voltage supply and a second reference voltage supply, and wherein one or more selection signals activate or de-activate one or more sub-counterbalance circuits of the plurality of sub-counterbalance circuits.

A system for obfuscating a first power consumption associated with one or more operations of a logic circuitry, the system comprising:

• a processor comprising:
• the logic circuitry;
• a counterbalance circuitry configured to provide a second power consumption to predictively counterbalance the first power consumption associated with the one or more operations of the logic circuitry, wherein the second power consumption varies inversely with the first power consumption associated with the one or more operations of the logic circuitry;
• and
• a header circuitry configured to enable the one or more operations of the logic circuitry, wherein the header circuitry and the counterbalance circuitry are configured to receive a selection signal;
• and
• a storage device for storing one or more instructions associated with the one or more operations of the logic circuitry,
• wherein the counterbalance circuitry comprises a plurality of sub-counterbalance circuits connected in parallel between a first reference voltage supply and a second reference voltage supply, and wherein one or more selection signals activate or de-activate one or more sub-counterbalance circuits of the plurality of sub-counterbalance circuits.