US 10,255,403 B1 · Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs

Abstract

A view definition analyzer maps a plurality of timing views for a circuit design into compatibility groups having shared operating conditions of their respective process corners. An ETM generator then extracts an extracted timing model from a block of the circuit design for each compatibility group, containing timing arcs representing each combination of interface path in the circuit block and timing view in the compatibility group, where at least one timing arc in the ETM is a merged version of multiple timing arcs for an interface path across multiple timing views in the compatibility group. Timing arcs are merged when each timing characteristic in a first timing arc matches, within a tolerance threshold, a corresponding timing characteristic in a second timing arc. The ETM may then be used to model any timing view in the compatibility group. The ETM generator thus produces a minimal set of extracted timing models.

Claims20

Dependent claims

A method of extracting a minimal set of extracted timing models (ETMs) for a plurality of timing views from a circuit block of a circuit design operable in a plurality of analysis modes under a plurality of corners, the circuit design representing an electronic circuit to be fabricated, the method comprising:

defining the plurality of timing views, each timing view representing a combination of at least one of a plurality of analysis modes with at least one of a plurality of corners, each corner defining a predetermined set of operating conditions for the electronic circuit;
executing a processor to selectively map, based at least on a compatibility test, the plurality of timing views to a plurality of compatibility groups, each of the plurality of timing views being mapped to at least one compatibility group;
and
for each compatibility group, executing a processor to extract an extracted timing model (ETM) of the circuit block for timing views mapped to said compatibility group,
wherein the compatibility test includes a comparison of the corners of at least a first and second timing view, wherein the compatibility test determines whether a new timing view is compatible with another timing view mapped in an existing compatibility group,
wherein the circuit design is altered to correct at least one timing violation detected by a static timing analysis of at least one ETM modeling the circuit block, and
wherein the electronic circuit is fabricated according to the altered circuit design.

4 more elements

A concurrent extracted timing model (ETM) generation system for generating models for a plurality of timing views from a circuit block of a circuit design operable in a plurality of analysis modes under a plurality of corners, the circuit design representing an electronic circuit to be fabricated, the system comprising:

a view definition analyzer configured to:
define a plurality of timing views, of timing views, each timing view representing a combination of at least one of a plurality of analysis modes with at least one of a plurality of corners, each corner defining a predetermined set of operating conditions for the electronic circuit, and
selectively map, based at least on a compatibility test, the plurality of timing views to a plurality of compatibility groups, each of the plurality of timing views being mapped to at least one compatibility group;
and
an ETM generator configured to extract an ETM for each compatibility group, the ETM modeling the circuit block for timing views mapped to said compatibility group,
wherein the compatibility test includes a comparison of the corners of at least a first and second timing view, wherein the compatibility test determines whether a new timing view is compatible with another timing view mapped in an existing compatibility group,
wherein the circuit design is altered to correct at least one timing violation detected by a static timing analysis of at least one ETM modeling the circuit block, and
wherein the electronic circuit is fabricated according to the altered circuit design.

5 more elements

A method of optimizing a static timing analysis (STA) process of a circuit design operable in a plurality of analysis modes under a plurality of corners, the circuit design representing an electronic circuit to be fabricated, the method comprising:

defining the plurality of timing views, each timing view representing a combination of at least one of a plurality of analysis modes with at least one of a plurality of corners, each corner defining a predetermined set of operating conditions for the electronic circuit,
executing a processor to selectively map, based at least on a compatibility test, the plurality of timing views to a plurality of compatibility groups, each of the plurality of timing views being mapped to at least one compatibility group;
for each compatibility group, executing a processor to extract an extracted timing model (ETM) of the circuit block for timing views mapped to said compatibility group;
and
executing a processor to perform at least one static timing analysis on the circuit design for all timing views mapped to a selected compatibility group by instantiating the ETM of the selected compatibility group in place of the circuit block in an analyzed circuit model,
wherein the compatibility test includes a comparison of the corners of at least a first and second timing view, wherein the compatibility test determines whether a new timing view is compatible with another timing view mapped in an existing compatibility group,
wherein the circuit design is altered to correct at least one timing violation detected by the static timing analysis, and
wherein the electronic circuit is fabricated according to the altered circuit design.

5 more elements

Dependencies are inferred from the claim text.

Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs

Life of this patent

Method and apparatus for concurrently extracting and validating timing models for different views in multi-mode multi-corner designs

Life of this patent

Abstract

Claims20