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US 10,255,400 B1Granted
Debugging system and method
AssigneeXilinx, Inc.
InventorsJason Villarreal, Xiaoyong Liu, Kumar Deepak
Life of this patent
Estimating the term…
Abstract
Disclosed approaches for configuring a memory include generating by a high-level synthesis (HLS) tool executing on a computer system, a first mapping of elements of a high-level language (HLL) program to elements of a hardware language finite state machine that represents a circuit implementation of the HLL program. The HLS tool further generates a second mapping of lines of the HLL program to states of the hardware language finite state machine and stores the information describing the first mapping and the second mapping in a data structure of a database in the memory.
Claims18
A method, comprising:
- storing a data structure in a memory of a data processing system for access by a debugging program executing on the data processing system;
- the data structure including information resident in a database used by the debugging program and including:
- a first mapping of elements of a high-level language (HLL) program to elements of a register transfer language (RTL) finite state machine that represents a circuit implementation of the HLL program;
- and
- a second mapping of line numbers of lines of the HLL program to states of the RTL finite state machine;
- determining by the debugging program from the second mapping, a state of the RTL finite state machine corresponding to line number in an HLL debugging command that specifies setting a breakpoint at the line number;
- setting the breakpoint on the state of the RTL state machine;
- simulating the circuit implementation of the HLL program using the RTL state machine;
- and
- suspending the simulation in response to activation of the state of the RTL finite state machine.
7 more elements
A method, comprising:
- generating by a high-level synthesis tool executing on a computer system, a first mapping of elements of a high-level language (HLL) program to elements of a register transfer language (RTL) finite state machine that represents a circuit implementation of the HLL program;
- generating by a hardware debug server, a second mapping of line numbers of lines of the HLL program to states of the RTL finite state machine;
- generating a third mapping of elements of the RTL finite state machine to locations of storage elements in a programmable integrated circuit (IC), wherein the locations of the storage elements correspond to the circuit implementation of the HLL program on the programmable IC;
- storing information describing the first mapping, the second mapping, and the third mapping in a data structure of a database in the memory;
- determining by a debugging program executing on a data processing system from the second mapping and the third mapping, a location of a storage element of the programmable IC corresponding to line number in an HLL debugging command that specifies setting a breakpoint at the line number;
- communicating the breakpoint and the location of the storage element to a debug controller circuit;
- operating the circuit implementation on the programmable IC;
- and
- suspending operation of the circuit implementation in response to the storage element having a value indicative of the breakpoint.
6 more elements
A debugging system, comprising:
- a programmable integrated circuit (IC), wherein the programmable IC is configured by a circuit implementation of a high-level language (HLL) program and a debug controller circuit;
- and
- a processor;
- and
- a memory arrangement coupled to the processor, wherein the memory arrangement is configured with instructions that when executed by the processor cause the processor to perform operations including:
- generating a first mapping of elements of the HLL program to elements of a register transfer language (RTL) finite state machine that represents a circuit implementation of the HLL program;
- generating a second mapping of line numbers of lines of the HLL program to states of the RTL finite state machine;
- generating a third mapping of elements of the RTL finite state machine to locations of storage elements in the programmable IC, wherein the locations of the storage elements correspond to the circuit implementation of the HLL program on the programmable IC;
- storing information describing the first mapping, the second mapping, and the third mapping in a data structure of a database in the memory;
- determining by a debugging program executing on a data processing system from the second mapping and the third mapping, a location of a storage element of the programmable IC corresponding to line number in an HLL debugging command that specifies setting a breakpoint at the line number;
- communicating the breakpoint and the location of the storage element to the debug controller circuit on the programmable IC;
- and
- wherein the debug controller circuit is configured to suspend operation of the circuit implementation of the HLL program in response to the storage element having a value indicative of the breakpoint.
10 more elements
Dependencies are inferred from the claim text.