Graphical analysis of complex clock trees

A system comprising:

• a memory device configured to store machine-readable instructions;
• and
• a computing system including one or more processing devices, in response to executing the machine-readable instructions, configured to:
• synthesize a clock tree in a layout design of an integrated circuit based, at least in part, on timing constraints for the integrated circuit;
• select a portion of the clock tree to present in a schematic connectivity presentation;
• generate the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree, which is coupled to at least one compacted representation of other portions of the clock tree in the schematic connectivity presentation of the clock tree;
• extract one or more clock tree circuits from the compacted representation based, at least in part, on a retained hierarchical connectivity of the other portions of the clock tree in the compacted representation;
• and
• modify the schematic connectivity presentation of the clock tree to include the extracted clock tree circuits coupled to a modified-version of the compacted representation that excludes the extracted clock tree circuits.

An apparatus including a memory device storing instructions configured to cause one or more processing devices to perform operations comprising:

• synthesizing a clock tree in a layout design of an integrated circuit based, at least in part, on timing constraints for the integrated circuit;
• selecting a portion of the clock tree to present in a schematic connectivity presentation;
• generating the schematic connectivity presentation of the clock tree that includes the selected portion of the clock tree, which is coupled to at least one compacted representation of other portions of the clock tree in the schematic connectivity presentation of the clock tree;
• extracting one or more clock tree circuits from the compacted representation based, at least in part, on a retained hierarchical connectivity of the other portions of the clock tree in the compacted representation;
• and
• modifying the schematic connectivity presentation of the clock tree to include the extracted clock tree circuits coupled to a modified-version of the compacted representation that excludes the extracted clock tree circuits.