Analyzing delay variations and transition time variations for electronic circuits

A computer system comprising:

• a processor;
• and
• a non-transitory computer readable storage medium configured to store instructions for operating an electronic design automation (EDA) tool set in a computing system, the instructions when executed by the processor cause the processor to:
• receive, by the EDA tool set, a digital representation of an electronic circuit, the electronic circuit comprising a plurality of cells;
• receive, by the EDA tool set, parameters describing an asymmetric distribution of delays associated with one or more cells of the electronic circuit, the parameters comprising:
• a nominal value of delays associated with the one or more cells,
• an early sigma value representing standard deviation of delay values smaller than the nominal value, and
• a late sigma value representing standard deviation of delay values larger than the nominal value;
• determine, by the EDA tool set, parameters of a normal distribution of delay values based on the parameters of the asymmetric distribution of delays;
• and
• perform, by the EDA tool set, statistical static timing analysis (SSTA) of the electronic circuit based on the parameters of the normal distribution of delay values associated with the electronic circuit;
• transmit, by the EDA tool set, results of the SSTA of the electronic circuit for presentation;
• apply, by the EDA tool set, modifications to the design of the integrated circuit responsive to sending the generated timing report for presentation;
• and
• transmit, by the EDA tool set, the modified design of the integrated circuit to a storage device to retrieve for manufacture of a circuit based on the design.

A computer-implemented method for operating an electronic design automation (EDA) tool set in a computing system, comprising:

• receiving, by the EDA tool set, a digital representation of an electronic circuit, the electronic circuit comprising a plurality of cells;
• receiving, by the EDA tool set, parameters describing an asymmetric distribution of delays associated with one or more cells of the electronic circuit, the parameters comprising:
• a nominal value of delays associated with the one or more cells,
• an early sigma value representing standard deviation of delay values smaller than the nominal value, and
• a late sigma value representing standard deviation of delay values larger than the nominal value;
• determining, by the EDA tool set, parameters of a normal distribution of delay values based on the parameters of the asymmetric distribution of delays, the determining comprising:
• determining a mean shift value based on the early sigma value and the late sigma value;
• and
• determining a nominal mean value for the normal distribution by adjusting the nominal value by the mean shift value;
• performing, by the EDA tool set, statistical static timing analysis (SSTA) of the electronic circuit based on the parameters of the normal distribution of delay values associated with the electronic circuit;
• transmitting, by the EDA tool set, results of the SSTA of the electronic circuit for presentation;
• applying, by the EDA tool set, modifications to the design of the integrated circuit responsive to sending the generated timing report for presentation;
• and
• transmitting, by the EDA tool set, the modified design of the integrated circuit to a storage device to retrieve for manufacture of a circuit based on the design.