Reduced overhead for massive parallel processing
AssigneeCadence Design Systems, Inc.
InventorsHarsh Vardhan, Jalal Wehbeh, Robert MacDonald
Life of this patent
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AssigneeCadence Design Systems, Inc.
InventorsHarsh Vardhan, Jalal Wehbeh, Robert MacDonald
Estimating the term…
A method for simulating an integrated circuit model is provided. The method includes receiving partition netlists of an integrated circuit in a partition scheduler and scheduling, by at least one computer, an execution of a computational thread associated with a first partition netlist. The method also includes preparing input data for a task and storing the input data set in an object storage. Also, the method includes executing, by the computer, the task in the computational thread. The method also includes building dependency trees between multiple tasks for reducing the input/output data overhead, and caching information that may be necessary for each task but may be reusable by the task when such information is unavailable from previously computed tasks.
A computer-implemented method for simulating an integrated circuit model, comprising:
A system, comprising:
A non-transitory, machine-readable medium comprising instructions stored in a memory which, when executed by a processor, cause a computer to perform steps in a method, the method comprising:
Dependencies are inferred from the claim text.