Enhanced PCIe storage device form factors

A storage assembly, comprising:

• a host input comprising at least one host PCIe interface that communicatively couples the storage assembly to a host system and receives input power for the storage assembly;
• a Peripheral Component Interconnect Express (PCIe) switch circuit communicatively coupled to PCIe interfaces of a plurality of storage device connectors and configured to receive storage operations over the host input issued by the host system and transfer the storage operations for delivery to ones of the plurality of storage device connectors over associated ones of the PCIe interfaces;
• a first circuit assembly comprising a first circuit assembly connector and at least three storage device connectors of the plurality of storage device connectors configured to mate with at least three corresponding storage devices, wherein at least the first circuit assembly connector is configured to carry signaling and power related to the at least three storage device connectors;
• and
• a second circuit assembly comprising a second circuit assembly connector and at least one further storage device connector of the plurality of storage device connectors configured to mate with at least one corresponding storage device, wherein at least the second circuit assembly connector is configured to mate with the first circuit assembly connector;
• and
• holdup circuitry configured to provide holdup power to at least a portion of the storage assembly after the input power is removed from the storage assembly by providing at least a first portion of the holdup power for delivery to the at least one further storage device connector on the second circuit assembly and at least a second portion of the holdup power for delivery to the at least three storage device connectors on the first circuit assembly.

A 2.5 inch form factor storage drive, comprising:

• a chassis configured structurally support elements of the storage drive;
• a U.2 connector for communication with a host system;
• three M.2 device connectors on a first circuit board configured to mate with associated M.2 devices;
• one M.2 device connector on a second circuit board configured to mate with an associated M.2 device;
• a PCIe switch circuit on the second circuit board communicatively coupled to the three M.2 device connectors on the first circuit board via at least an internal connector coupling the first circuit board with the second circuit board;
• the PCIe switch circuit further communicatively coupled to the one M.2 device connector on the second circuit board and the U.2 connector, wherein the PCIe switch circuit is configured to receive operations over the U.2 connector and transfer the operations for delivery to ones of the M.2 device connectors over associated PCIe interfaces.