Method and apparatus for sub-page write protection

A method comprising:

• performing a page walk using a guest physical address (GPA) and detecting, by checking one or more sub-page permission bits within a memory page table, whether a page identified with the GPA is mapped with the one or more sub-page permission bits that indicate walking a sub-page protection table being enabled for the page, and wherein the sub-page protection table indicates read and write permissions of sub-pages;
• storing at least one GPA and other sub-page-related data including an offset and operand size for the GPA in a sub-page control storage;
• determining whether the GPA is identified in the sub-page control storage;
• sending a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a match against data programmed in the sub-page control storage when there is a TLB hit, the sub-page protection indication indicating the translation is for a sub-page TLB entry;
• matching the offset and operand size for the GPA in the sub-page control storage, if TLB entry has a sub-page protection indication;
• invoking one or more microcode assist operations to perform fault checking if there is no match of the offset and/or operand size;
• and
• caching write-permission bits for the GPA into a write-allowed scratchpad register when the one or more microcode assist operations are invoked.

A system comprising:

• a memory to store program code and data;
• a processor to process the program code and data to implement a virtual machine monitor (VMM) and one or more guest operating systems (OSs) executed within one or more virtual machines (VMs) supported by the VMM, the guest OSs to utilize guest physical addresses (GPAs) to perform memory operations, the GPAs to be translated by the VMMs;
• the processor further comprising:
• a memory management unit implemented in a circuit, including a page miss handler to perform a page walk using a GPA and to detect, by checking one or more sub-page permission bits within a memory page table, whether a page identified with the GPA is mapped with the one or more sub-page permission bits that indicate walking a sub-page protection table being enabled for the page, and wherein the sub-page protection table indicates read and write permissions of sub-pages,
• a sub-page control storage to store at least one GPA and other sub-page related data including an offset and operand size for the GPA;
• and
• a write-allowed scratchpad register,
• wherein the page miss handler is to determine whether the GPA is identified in the sub-page control storage, and
• the page miss handler is to send a translation to a translation lookaside buffer (TLB) with a sub-page protection indication set to cause a matching of the sub-page related data when there is a TLB hit, the sub-page protection indication indicating the translation is for a sub-page TLB entry, wherein the TLB is further configured to match the offset and operand size for the GPA in the sub-page control storage, if a TLB entry with the sub-page protection indication was hit for an access, and wherein the TLB is to invoke one or more microcode assist operations to perform fault checking if there is no match of the offset and/or operand size when an access matches a TLB entry with sub-page protection indication, and
• wherein when the one or more microcode assist operations are invoked by the page miss handler, the one or more microcode assist operations cache write-permission bits for the GPA into the write-allowed scratchpad register.