US 10,255,191 B2Granted

Logical memory address regions

AssigneeAdvanced Micro Devices, Inc.

InventorsAmin Farmahini-Farahani, David A. Roberts

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Abstract

Systems, apparatuses, and methods for implementing logical memory address regions in a computing system. The physical memory address space of a computing system may be partitioned into a plurality of logical memory address regions. Each logical memory address region may be dynamically configured at run-time to meet changing application needs of the system. Each logical memory address region may also be configured separately from the other logical memory address regions. Each logical memory address region may have associated parameters that identify region start address, region size, cell-level mode, physical-to-device mapping scheme, address masks, access permissions, wear-leveling data, encryption settings, and compression settings. These parameters may be stored in a table which may be used when processing memory access requests.

Claims20

Dependent claims

An apparatus, comprising:

one or more processors;
a memory controller;
and
one or more memory devices;
wherein the apparatus is configured to:
partition a physical memory address space of the one or more memory devices into a plurality of logical memory address regions;
assign a first application to a first logical memory address region of the plurality of logical memory address regions;
program, into a table, a first plurality of attributes to be applied to the first logical memory address region, wherein the first plurality of attributes are optimized for memory access patterns of the first application;
program, into the table, a second plurality of attributes to be applied to a second logical memory address region of the plurality of logical memory address regions, wherein at least a first attribute of the first plurality of attributes is different from a corresponding attribute of the second plurality of attributes;
and
utilize the first plurality of attributes for determining how to process a first memory request targeting the first logical memory address region.

8 more elements

A method, comprising:

partitioning a physical memory address space of one or more memory devices into a plurality of logical memory address regions;
assign a first application to a first logical memory address region of the plurality of logical memory address regions;
programming, into a table, a first plurality of attributes to be applied to the first logical memory address region, wherein the first plurality of attributes are optimized for memory access patterns of the first application;
programming, into the table, a second plurality of attributes to be applied to a second logical memory address region of the plurality of logical memory address regions, wherein at least a first attribute of the first plurality of attributes is different from a corresponding attribute of the second plurality of attributes;
and
utilizing the first plurality of attributes for determining how to process a first memory request targeting the first logical memory address region.

3 more elements

A system, comprising:

one or more memory devices;
and
a processor;
wherein the processor is configured to execute program instructions configured to:
partition a physical memory address space of the one or more memory devices into a plurality of logical memory address regions;
assign a first application to a first logical memory address region of the plurality of logical memory address regions;
program, into a table, a first plurality of attributes to be applied to the first logical memory address region, wherein the first plurality of attributes are optimized for memory access patterns of the first application;
program, into the table, a second plurality of attributes to be applied to a second logical memory address region of the plurality of logical memory address regions, wherein at least a first attribute of the first plurality of attributes is different from a corresponding attribute of the second plurality of attributes;
and
utilize the first plurality of attributes for determining how to process a first memory request targeting the first logical memory address region.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/133,033Filed 19 Apr 2016 · us provisional application
Priority: 13 Aug 2015
Published: US 2017/0046272 A116 Feb 2017
Granted: 9 Apr 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification12 codes

G06F 12/1009
Address translation: using page tables, e.g. page table structures
G06F 12/0238
Free address space management: memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
G06F 12/1408
Protection against unauthorised use of memory or access to memory: by using cryptography
G06F 12/1441
The protection being physical, e.g. cell, word, block: for a range