Hybrid cache
AssigneeAdvanced Micro Devices, Inc.
InventorGabriel H. Loh
Life of this patent
Estimating the term…
Abstract
Systems, apparatuses, and methods for implementing a hybrid cache. A processor may include a hybrid L2/L3 cache which allows the processor to dynamically adjust a size of the L2 cache and a size of the L3 cache. In some embodiments, the processor may be a multi-core processor and there may be a single cache partitioned into a logical L2 cache and a logical L3 cache for use by the cores. In one embodiment, the processor may track the cache hit rates of the logical L2 and L3 caches and adjust the sizes of the logical L2 and L3 cache based on the cache hit rates. In another embodiment, the processor may adjust the sizes of the logical L2 and L3 caches based on which application is currently being executed by the processor.
Claims19
A processor comprising:
- a first physical cache coupled to a first core;
- a second physical cache coupled to a second core;
- and
- a control unit;
- wherein the control unit is configured to:
- partition the first physical cache into a first logical cache and a first portion of a second logical cache;
- partition the second physical cache into a third logical cache and a second portion of the second logical cache, wherein the first and the third logical caches represent a first level of a cache hierarchy, and wherein the second logical cache represents a second level of the cache hierarchy, and wherein each of the first logical cache and second logical cache are configured to store data retrieved from a higher level memory;
- reallocate a first way of the second logical cache to the first logical cache;
- identify a first cacheline stored in the first way of the second logical cache;
- and
- invalidate the first cacheline responsive to reallocating the first way from the second logical cache to the first logical cache.
A method, comprising:
- partitioning a first physical cache coupled to a first core into a first logical cache and a first portion of a second logical cache;
- and
- partitioning a second physical cache coupled to a second core into a third logical cache and a second portion of the second logical cache, wherein the first and the third logical caches represent a first level of a cache hierarchy, wherein the second logical cache represents a second level of the cache hierarchy, and wherein each of the first logical cache and second logical cache are configured to store data retrieved from a higher level memory;
- reallocating a first way of the second logical cache to the first logical cache;
- identifying a first cacheline stored in the first way of the second logical cache;
- and
- invalidating the first cacheline responsive to reallocating the first way from the second logical cache to the first logical cache.
A system comprising:
- a memory;
- and
- a processor comprising:
- a first physical cache coupled to a first core;
- a second physical cache coupled to a second core;
- and
- a control unit;
- wherein the control unit is configured to:
- partition the first physical cache into a first logical cache and a first portion of a second logical cache;
- partition a second physical cache coupled to a second core into a third logical cache and a second portion of the second logical cache, wherein the first and the third logical caches represent a first level of a cache hierarchy, and wherein the second logical cache represents a second level of the cache hierarchy, and wherein each of the first logical cache and second logical cache are configured to store data retrieved from the memory;
- reallocate a first way of the second logical cache to the first logical cache;
- identify a first cacheline stored in the first way of the second logical cache;
- and
- invalidate the first cacheline responsive to reallocating the first way from the second logical cache to the first logical cache.
Dependencies are inferred from the claim text.