US 10,255,186 B2Granted

Approximate cache memory

AssigneePurdue Research Foundation

InventorsAshish Ranjan, Swagath Venkataramani, Zoha Pajouhi, Rangharajan Venkatesan, Kaushik Roy, Anand Raghunathan

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Abstract

An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

Claims20

Dependent claims

An approximate cache system, comprising:

a quality aware cache controller (QACC) configured to receive address, data, and a read/write signal from a processor;
a cache, including
a data array comprising one or more ways, each way having one or more bytes, and each byte having one or more bit groups, and
a tag array comprising one or more ways each associated with the one or more ways of the data array;
and
a quality table configured to receive addresses and a quality specification from the processor associated with each address, the quality specification corresponding to one or more of (i) permissible magnitude of error, (ii) error rate, and (iii) average error associated with data held in each address, the quality table further configured to provide the quality specification for each address to the QACC,
wherein the QACC controls acceptable error at runtime based on maximizing energy savings vs minimizing introduced error by selectively choosing one or more of i) partial read operations, where one or more least significant bits (LSBs) of the address are ignored for reading by being set to a constant;
ii) lower read current operations, where a current smaller than a predetermined read current for an error-free read is passed through bit-cells of data array;
iii) skipped write operations, where a write to an address can be skipped based on whether the skipped write would violate the quality specification;
iv) partial write operations, where one or more least significant bits (LSBs) of the address are ignored for writing;
v) lower write duration operations, where a current duration shorter than a predetermined write current duration for an error-free write is passed through bit-cells of the data array;
vi) lower write current operations, where a current smaller than a predetermined write current for an error-free write is passed through bit-cells of data array;
and vii) skipped refresh operations, where refreshes are skipped for cache blocks that have been written a predetermined time ago.

10 more elements

A method of controlling cache using approximation, comprising:

providing a quality aware cache controller (QACC) configured to receive address, data, and a read/write signal from a processor;
providing a cache, including
a data array comprising one or more ways, each way having one or more bytes, and each byte having one or more bit groups, and
a tag array comprising one or more ways each associated with the one or more ways of the data array;
and
providing a quality table configured to receive addresses and a quality specification from the processor associated with each address, the quality specification corresponding to one or more of (i) permissible magnitude of error, (ii) error rate, and (iii) average error associated with data held in each address, the quality table further configured to provide the quality specification for each address to the QACC,
wherein the QACC controls acceptable error at runtime based on maximizing energy savings vs. minimizing introduced error by selectively choosing one or more of i) partial read operations, where one or more least significant bits (LSBs) of the address are ignored for reading by being set to a constant;
ii) lower read current operations, where a current smaller than a predetermined read current for an error-free read is passed through bit-cells of data array;
iii) skipped write operations, where a write to an address can be skipped based on whether the skipped write would violate the quality specification;
iv) partial write operations, where one or more least significant bits (LSBs) of the address are ignored for writing;
v) lower write duration operations, where a current duration shorter than a predetermined write current duration for an error-free write is passed through bit-cells of the data array;
vi) lower write current operations, where a current smaller than a predetermined write current for an error-free write is passed through bit-cells of data array;
and vii) skipped refresh operations, where refreshes are skipped for cache blocks that have been written a predetermined time ago.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/623,343Filed 14 Jun 2017
Published: US 2018/0365154 A120 Dec 2018
Granted: 9 Apr 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G06F 12/0848
Cache with multiple tag or data arrays being simultaneously accessible: partitioned cache, e.g. separate instruction and operand caches
G06F 12/0846
Multiple simultaneous or quasi-simultaneous cache accessing: cache with multiple tag or data arrays being simultaneously accessible
G06F 12/0864
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…
G06F 12/0891
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: using…