Memory access architecture with coherence

A method for transferring data in a computer system with a set of processor chips comprising a plurality of processor chips and a set of memory buffer chips comprising a plurality of memory buffer chips, each of the processor chips being communicatively coupled to at least one memory module configured for storing memory lines and assigned to the processor chip, each of the processor chips comprising a cache configured for caching memory lines, each of the processor chips being communicatively coupled to each of the memory buffer chips via a memory-buffer-chip-specific bidirectional point-to-point communication connection, at least one of the memory buffer chips comprising a coherence directory and being configured for being exclusively in charge for implementing directory-based coherence over the caches of the processor chips for at least one pre-defined address-based subset of memory lines stored in at least one of the memory modules assigned to one of the processor chips, the method comprising:

• transferring by the processor chip assigned to the at least one memory module a memory line of the subset of memory lines between the at least one memory module and the cache of one of the remaining processor chips of the set of processor chips using the memory buffer chip in charge for implementing the coherence for the subset of memory lines as a transfer node and updating by the memory buffer chip the coherence directory regarding the transfer of the memory lines.