Dynamic input/output coherency
AssigneeQUALCOMM Incorporated
InventorsAndrew Edmund Turner, Bohuslav Rychlik
Life of this patent
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Abstract
Aspects include computing devices, apparatus, and methods implemented by the apparatus for implementing dynamic input/output (I/O) coherent workload processing on a computing device. Aspect methods may include offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode, detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator, and switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator.
Claims26
A method of implementing dynamic input/output (I/O) coherent workload processing on a computing device, comprising:
- offloading, by a processing device, a workload to a hardware accelerator for execution using an I/O coherent mode;
- detecting, by the processing device, a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator;
- executing a cache flush maintenance operation for a cache of the processing device in parallel with execution of the workload by the hardware accelerator in response to detecting the dynamic trigger for switching from the I/O coherent mode to the non-I/O coherent mode;
- and
- switching from the I/O coherent mode to the non-I/O coherent mode while the workload is executed by the hardware accelerator in response to completion of the cache flush maintenance operation.
A computing device, comprising:
- a shared memory;
- a hardware accelerator;
- and
- a processor device coupled to the shared memory and the hardware accelerator, and configured with processor-executable software instructions to:
- offload a workload to the hardware accelerator for execution using an I/O coherent mode;
- detect a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator;
- execute a cache flush maintenance operation for a cache of the processing device in parallel with execution of the workload by the hardware accelerator in response to detecting the dynamic trigger for switching from the I/O coherent mode to the non-I/O coherent mode;
- and
- switch from the I/O coherent mode to the non-I/O coherent mode while the workload is executed by the hardware accelerator in response to detecting the dynamic completion of the cache flush maintenance operation.
A computing device, comprising:
- a hardware accelerator;
- means for offloading a workload to the hardware accelerator for execution using an I/O coherent mode;
- means for detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator;
- means for executing a cache flush maintenance operation for a cache in parallel with execution of the workload by the hardware accelerator in response to detecting the dynamic trigger for switching from the I/O coherent mode to the non-I/O coherent mode;
- and
- means for switching from the I/O coherent mode to the non-I/O coherent mode while the workload is executed by the hardware accelerator in response to detecting the dynamic trigger completion of the cache flush maintenance operation.
A non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a processing device of a computing device to perform operations comprising:
- offloading a workload to a hardware accelerator for execution using an I/O coherent mode;
- detecting a dynamic trigger for switching from the I/O coherent mode to a non-I/O coherent mode while the workload is executed by the hardware accelerator;
- executing a cache flush maintenance operation for a cache of the processing device in parallel with execution of the workload by the hardware accelerator in response to detecting the dynamic trigger for switching from the I/O coherent mode to the non-I/O coherent mode;
- and
- switching from the I/O coherent mode to the non-I/O coherent mode while the workload is executed by the hardware accelerator in response to completion of the cache flush maintenance operation.
Dependencies are inferred from the claim text.