Back to results
US 10,255,150 B2Granted
Multichip debugging method and multichip system adopting the same
AssigneeSamsung Electronics Co., Ltd.
InventorsJong-min Kim, Chan-ho Yoon, Jung-pil Lee, Hyung-joon Park, Jae-ho Sim
Life of this patent
Estimating the term…
Abstract
Provided are a multichip debugging method and a multichip system adopting the same. The multichip system includes: a first chip including a first debugging port and first identification (ID) information, a second chip including a second debugging port and second ID information, and a test access port (TAP) electrically connected to the first debugging port and the second debugging port and configured to connect to a test apparatus via the TAP.
Claims15
A multichip system comprising:
- a first chip comprising a first debugging port and first identification (ID) information;
- a second chip comprising a second debugging port and second ID information;
- and
- a test access port (a TAP) electrically connected to the first debugging port and the second debugging port, and configured to connect to a test apparatus via the TAP,
- wherein the first chip and the second chip are configured to perform a debugging process based on a multi-drop method,
- wherein the first chip and the second chip are arranged on a printed circuit board (a PCB),
- the first chip comprises a first ID information port including a first plurality of terminals;
- and
- the second chip comprises a second ID information port including a second plurality of terminals, and
- a circuit on the PCB is configured to pull up or pull down the first ID information to the first plurality of terminals and the second ID information to the second plurality of terminals.
7 more elements
A multichip debugging method comprising:
- allocating first identification (ID) information to a first chip of a plurality of chips arranged on a printed circuit board (a PCB) and second ID information to a second chip of the plurality of chips;
- receiving target chip ID information via a test access port (a TAP) electrically connected to a first debugging port of the first chip and a second debugging port of the second chip;
- selecting one among the first chip and the second chip as a target chip to be tested based on the target chip ID information received via the TAP;
- and
- performing a debugging process on the target chip,
- wherein the first chip comprises a first ID information port including a first plurality of terminals,
- the second chip comprises a second ID information port including a second plurality of terminals, and
- the selecting the target chip comprises pulling up or pulling down the first ID information to the first plurality of terminals and the second ID information to the second plurality of terminals.
5 more elements
A chip comprising:
- a debugging port configured to communicate with a test apparatus;
- an ID information port including a plurality of terminals;
- and
- a processor configured to compare ID information indicating a plurality of bits received via the debugging port with ID information identifying the chip, determine whether the received ID information indicates the chip based on the comparison, and control the chip to perform a debugging operation based on the determining,
- wherein the chip is arranged on a printed circuit board (a PCB), and
- a circuit on the PCB is configured to pull up or pull down the ID information identifying the chip to the plurality of terminals.
3 more elements
Dependencies are inferred from the claim text.