System and method for protecting GPU memory instructions against faults
AssigneeAdvanced Micro Devices, Inc.
InventorsJohn Kalamatianos, Michael Mantor, Sudhanva Gurumurthi
Life of this patent
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Abstract
A system and method for protecting memory instructions against faults are described. The system and method include converting the slave instructions to dummy operations, modifying memory arbiter to issue up to N master and N slave global/shared memory instructions per cycle, sending master memory requests to memory system, using slave requests for error checking, entering master requests to the GM/LM FIFO, storing slave requests in a register, and comparing the entered master requests with the stored slave requests.
Claims21
A system for protecting memory instructions against faults, the system comprising:
- a memory arbiter that selects a master/slave memory instruction pair to issue responsive to a memory request, wherein the master instruction and the slave instruction are executed in lockstep;
- a data cache that receives the master instruction and allows access by at least two single instruction multiple data (SIMD) processors to complete the memory access for both the master and slave memory instructions;
- a data error check logic that receives master and slave instruction data and performs data error check logic error checking between the master and slave operations;
- and
- a memory data that receives master data from the data error check logic and utilizes parity information from the master instruction to check for errors.
A method for protecting memory instructions against faults, the method comprising:
- selecting a master instruction and the master's slave instruction via a memory arbiter responsive to a memory request;
- executing the master instruction and slave instruction in lockstep;
- checking for errors between master and slave instruction using at least one error check logic;
- and
- completing the memory access to the master and slave instructions by returning data/status at least two SIMDs.
A computer readable non-transitory medium including instructions which when executed in a processing system cause the processing system to execute a method for protecting memory instructions against faults, the method comprising:
- selecting a master instruction and the master's slave instruction via a memory arbiter responsive to a memory request;
- executing the master instruction and slave instruction in lockstep;
- checking for errors between master and slave instruction using at least one error check logic;
- and
- completing the memory access to the master and slave instructions by returning data/status at least two SIMDs.
Dependencies are inferred from the claim text.