Operation of a multi-slice processor implementing a load/store unit maintaining rejected instructions

Abstract

Operation of a multi-slice processor that includes a plurality of execution slices, a plurality of load/store slices, and one or more instruction sequencing units, where operation includes: receiving, at a load/store slice from an instruction sequencing unit, a instruction to be issued; determining, at the load/store slice, a rejection condition for the instruction; and responsive to determining the rejection condition for the instruction, maintaining state information for the instruction in the load/store slice instead of notifying the instruction sequencing unit of a rejection of the instruction.

Dependencies are inferred from the claim text.