Adaptive CPU NUMA scheduling
AssigneeVMware, Inc.
InventorsSeongbeom Kim, Haoqiang Zheng, Rajesh Venkatasubramanian, Puneet Zaroo
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AssigneeVMware, Inc.
InventorsSeongbeom Kim, Haoqiang Zheng, Rajesh Venkatasubramanian, Puneet Zaroo
Estimating the term…
Systems and methods for performing selection of non-uniform memory access (NUMA) nodes for mapping of virtual central processing unit (vCPU) operations to physical processors are provided. A CPU scheduler evaluates the latency between various candidate processors and the memory associated with the vCPU, and the size of the working set of the associated memory, and the vCPU scheduler selects an optimal processor for execution of a vCPU based on the expected memory access latency and the characteristics of the vCPU and the processors. The systems and methods further provide for monitoring system characteristics and rescheduling the vCPUs when other placements provide improved performance and efficiency.
A system for assigning a process to one of a set of non-uniform memory access (NUMA) nodes comprising a first NUMA node and a second NUMA node, the first NUMA node and the second NUMA node each including a destination central processing unit (CPU) and a memory, the system comprising:
A method for assigning a process to one of a set of non-uniform memory access (NUMA) nodes comprising a first NUMA node and a second NUMA node, first NUMA node and the second NUMA node each including a destination central processing unit (CPU) and a memory, the method comprising:
One or more non-transitory computer-readable storage media including computer-executable components for assigning a process to one of a set of non-uniform memory access (NUMA) nodes comprising a first NUMA node and a second NUMA node, the first NUMA node and the second NUMA node each including a destination central processing unit (CPU) and a memory, the computer-executable components comprising:
Dependencies are inferred from the claim text.