Operating a pipeline flattener in order to track instructions for complex breakpoints
AssigneeTexas Instruments Incorporated
InventorsMarkus Koesler, Johann Zipperer, Christian Wiencke, Wolfgang Lutsch
Life of this patent
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Abstract
A semiconductor device comprising a processor having a pipelined architecture and a pipeline flattener and a method for operating a pipeline flattener in a semiconductor device are provided. The processor comprises a pipeline having a plurality of pipeline stages and a plurality of pipeline registers that are coupled between the pipeline stages. The pipeline flattener comprises a plurality of trigger registers for storing a trigger, wherein the trigger registers are coupled between the pipeline stages.
Claims18
A semiconductor device comprising:
- a processor having a pipelined architecture and a pipeline flattener;
- wherein the processor comprises:
- a pipeline having a plurality of pipeline stages;
- and
- a plurality of pipeline registers which are coupled between the pipeline stages, each pipeline register being associated with a respective one of the pipeline stages;
- wherein the pipeline flattener comprises:
- a plurality of trigger registers each configured to store a trigger, wherein the trigger registers are coupled between the pipeline stages and each trigger register is associated with a respective one of the pipeline stages;
- wherein the pipeline flattener is configured to:
- set the trigger stored by the trigger register associated with a pipeline stage receiving an instruction to a trigger value equal to one of a first predetermined trigger value indicating that the received instruction is selected for debug tracking and a second predetermined trigger value indicating that the received instruction is not selected for debug tracking;
- forward the trigger through trigger registers associated with pipeline stages subsequent to the pipeline stage receiving the instruction in synchrony with movement of the received instruction through the pipeline;
- determine whether the trigger indicates the first predetermined trigger value or the second predetermined trigger value;
- and
- provide tracked debug data to a debug unit of the semiconductor device when the trigger indicates the first predetermined trigger value and not provide tracked debug data to the debug unit when the trigger indicates the second predetermined trigger value.
A method for operating in a semiconductor device having a processor including a pipelined architecture with a plurality of pipeline stages and a plurality of pipeline registers coupled between the pipeline stages with each pipeline register being associated with a respective one of the pipeline stages and a pipeline flattener including a plurality of trigger registers coupled between the pipeline stages with each trigger register being associated with a respective one of the pipeline stages and configured to store a trigger, the method comprising:
- setting the trigger stored by the trigger register associated with a pipeline stage receiving an instruction to a trigger value equal to one of a first predetermined trigger value indicating that the received instruction is selected for debug tracking and a second predetermined trigger value indicating that the received instruction is not selected for debug tracking;
- forwarding the trigger through trigger registers associated with pipeline stages subsequent to the pipeline stage receiving the instruction in synchrony with movement of the received instruction through the pipeline;
- determining whether the trigger indicates the first predetermined trigger value or the second predetermined trigger value;
- and
- providing tracked debug data to a debug unit of the semiconductor device when the trigger indicates the first predetermined trigger value and not providing tracked debug data to the debug unit when the trigger indicates the second predetermined trigger value.
Dependencies are inferred from the claim text.