US 10,255,077 B2Granted

Apparatus and method for a hybrid latency-throughput processor

AssigneeIntel Corporation

InventorsOren Ben-Kiki, Yuval Yosef, Ilan Pardo, Dror Markovich

Life of this patent

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Abstract

An apparatus and method are described for executing both latency-optimized execution logic and throughput-optimized execution logic on a processing device. For example, a processor according to one embodiment comprises: latency-optimized execution logic to execute a first type of program code; throughput-optimized execution logic to execute a second type of program code, wherein the first type of program code and the second type of program code are designed for the same instruction set architecture; logic to identify the first type of program code and the second type of program code within a process and to distribute the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.

Claims9

Dependent claims

A method comprising:

providing, by a first processing unit, latency-optimized execution logic to execute a first type of program code;
providing, by a second processing unit, throughput-optimized execution logic to execute a second type of program code, the throughput-optimized execution logic comprising a plurality of processing elements (PEs), each PE adapted to execute the second type of program code, the first type of program code and the second type of program code designed for the same instruction set architecture;
and
identifying, by one of the first or second processing units, the first type of program code and the second type of program code within a process and responsively distributing the first type of program code for execution on the latency-optimized execution logic and the second type of program code for execution on the throughput-optimized execution logic.

1 more element

Dependencies are inferred from the claim text.

Facts

Application: 15/226,875Filed 2 Aug 2016 · continuation
Priority: 28 Dec 2012
Published: US 2016/0342419 A124 Nov 2016
Granted: 9 Apr 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G06F 9/30079
To perform miscellaneous control operations, e.g. NOP: pipeline control instructions, e.g. multicycle NOP
G06F 9/3836
Concurrent instruction execution, e.g. pipeline or look ahead: instruction issuing, e.g. dynamic instruction scheduling or out of order…
G06F 9/3851
Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution: from multiple instruction streams, e.g. multistreaming
G06F 9/3856
Instruction completion, e.g. retiring, committing or graduating: reordering of instructions, e.g. using queues or age tags

Family

Application13/730,055Parent of this continuation · filed 28 Dec 2012
US 2016/0342419 A1Pre-grant publication · published 24 Nov 2016
US 9,417,873 B2Parent of this continuation
US 2014/0189317 A1Published application
US 10,255,077 B2This patent

From the US filing history. Foreign family members aren’t listed.