Method for performing dual dispatch of blocks and half blocks
AssigneeIntel Corporation
InventorMohammad Abdallah
Life of this patent
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Abstract
A method by a processor for performing multi-dispatch of instruction blocks. The method includes receiving an incoming sequence of instructions, grouping the instructions to form instruction blocks including a first instruction block, and performing a multi-dispatch of the first instruction block for execution on one or more execution units by dispatching the first instruction block multiple times, wherein different instructions within the first instruction block are executed for each dispatch.
Claims18
A method by a processor for performing multi-dispatch of instruction blocks, the method comprising:
- receiving an incoming sequence of instructions;
- grouping the instructions to form instruction blocks including a first instruction block;
- and
- performing a multi-dispatch of the first instruction block for execution on one or more execution units by dispatching the first instruction block multiple times in multiple processor cycles in response to a determination that instructions within the first instruction block cannot be dispatched within a single processor cycle, wherein different instructions within the first instruction block are executed for each dispatch.
A processor comprising:
- a fetch unit to receive an incoming sequence of instructions;
- a scheduler to group the instructions to form instruction blocks including a first instruction block;
- one or more execution units to execute instructions;
- and
- a dispatcher to perform a multi-dispatch of the first instruction block for execution on the one or more execution units by dispatching the first instruction block multiple times in multiple processor cycles in response to a determination that instructions within the first instruction block cannot be dispatched within a single processor cycle, wherein different instructions within the first instruction block are executed for each dispatch.
A computer system comprising:
- a memory;
- and
- a processor comprising
- a fetch unit to receive an incoming sequence of instructions,
- a scheduler to group the instructions to form instruction blocks including a first instruction block,
- one or more execution units to execute instructions, and
- a dispatcher to perform a multi-dispatch of the first instruction block for execution on the one or more execution units by dispatching the first instruction block multiple times in multiple processor cycles in response to a determination that instructions within the first instruction block cannot be dispatched within a single processor cycle, wherein different instructions within the first instruction block are executed for each dispatch.
Dependencies are inferred from the claim text.