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US 10,255,075 B2Granted
System, method, and computer program product for managing out-of-order execution of program instructions
AssigneeNVIDIA Corporation
InventorsOlivier Giroux, Robert Ohannessian, Jr., Jack H. Choquette, William Parsons Newhall, Jr.
Life of this patent
Estimating the term…
Abstract
A method, system and computer program product embodied on a computer-readable medium are provided for managing the execution of out-of-order instructions. The method includes the steps of receiving a plurality of instructions and identifying a subset of instructions in the plurality of instructions to be executed out-of-order.
Claims20
A method, comprising:
- receiving a plurality of instructions by a processor;
- identifying, by a scheduler unit within the processor, a subset of instructions in the plurality of instructions to be executed out-of-order by inspecting metadata associated with the plurality of instructions;
- and
- for each instruction in the subset of instructions, the scheduler unit adds the instruction to a virtual queue specified by metadata for the instruction, wherein the virtual queue is one of a plurality of virtual queues implemented in an on-chip random access memory (RAM), and wherein each virtual queue in the plurality of virtual queues is implemented as a circular FIFO in the RAM.
1 more element
A non-transitory computer-readable storage medium storing instructions that, when executed by a processor, cause the processor to perform steps comprising:
- receiving a plurality of instructions by the processor;
- identifying, by a scheduler unit within the processor, a subset of instructions in the plurality of instructions to be executed out-of-order by inspecting metadata associated with the plurality of instructions;
- and
- for each instruction in the subset of instructions, the scheduler unit adds the instruction to a virtual queue specified by metadata for the instruction, wherein the virtual queue is one of a plurality of virtual queues implemented in an on-chip random access memory (RAM), and wherein each virtual queue in the plurality of virtual queues is implemented as a circular FIFO in the RAM.
1 more element
A system, comprising:
- a processor configured to:
- receive a plurality of instructions;
- identify, by a scheduler unit within the processor, a subset of instructions in the plurality of instructions to be executed out-of-order by inspecting metadata associated with the plurality of instructions;
- and
- for each instruction in the subset of instructions, the scheduler unit adds the instruction to a virtual queue specified by metadata for the instruction, wherein the virtual queue is one of a plurality of virtual queues implemented in an on-chip random access memory (RAM), and wherein each virtual queue in the plurality of virtual queues is implemented as a circular FIFO in the RAM.
2 more elements
Dependencies are inferred from the claim text.