US 10,255,074 B2 · Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt

Abstract

Selective flushing of instructions in an instruction pipeline in a processor back to an execution-determined target address in response to a precise interrupt is disclosed. A selective instruction pipeline flush controller determines if a precise interrupt has occurred for an executed instruction in the instruction pipeline. The selective instruction pipeline flush controller determines if an instruction at the correct resolved target address of the instruction that caused the precise interrupt is contained in the instruction pipeline. If so, the selective instruction pipeline flush controller can selectively flush instructions back to the instruction in the pipeline that contains the correct resolved target address to reduce the amount of new instruction fetching. In this manner, as an example, the performance penalty of precise interrupts can be lessened through less instruction refetching and reduced delay in instruction pipeline refilling when the instruction containing the correct target address is already contained in the pipeline.

Claims30

Dependent claims

A controller for a processor, the controller configured to:

receive, from an instruction processing system, a precise interrupt, comprising a resolved target address of a first instruction within an instruction pipeline in the instruction processing system, as a result of a hazard generated by executing the first instruction;
responsive to receiving the precise interrupt, determine whether a second instruction at the resolved target address is present in the instruction pipeline in the instruction processing system;
and
responsive to determining that the second instruction at the resolved target address is present in the instruction pipeline, flush at least one instruction fetched subsequent to the first instruction and prior to the second instruction in the instruction pipeline.

1 more element

An instruction processing system for a processor comprising:

one or more instruction pipelines each comprising an instruction fetch circuit configured to fetch instructions from an instruction memory into an instruction pipeline queue, and an execution circuit configured to execute the fetched instructions in the instruction pipeline queue;
and
a controller configured to:
receive a precise interrupt comprising a resolved target address of a first instruction within an instruction pipeline of the one or more instruction pipelines in the instruction processing system, as a result of a hazard generated by executing the first instruction;
response to receiving the precise interrupt, determine whether a second instruction at the resolved target address is present in the instruction pipeline of the one or more instruction pipelines in the instruction processing system;
and
responsive to determining that the second instruction at the resolved target address is present in the instruction pipeline, flush at least one instruction fetched subsequent to the first instruction and prior to the second instruction in the instruction pipeline.

4 more elements

Dependencies are inferred from the claim text.

Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt

Life of this patent

Selective flushing of instructions in an instruction pipeline in a processor back to an execution-resolved target address, in response to a precise interrupt

Life of this patent

Abstract

Claims30