Microcontroller with variable length move instructions using direct immediate addressing or indirect register offset addressing

Abstract

An 8-bit microprocessor has a program memory having a 16-bit instruction word size and a data memory having an 8-bit data size. An instruction word has a payload size for an address of up to 12 bits. The microprocessor furthermore has a central processing unit coupled with the program memory and the data memory, a bank select register configured to select one of up to 64 memory banks, and an indirect addressing register operable to address up to 16KB of data memory. The CPU is configured to execute a first move instruction having two instruction words and being configured to only access the lower 4KB of the data memory and a second move instruction having three instruction words and configured to access the entire data memory.

Dependencies are inferred from the claim text.