Architectural register replacement for instructions that use multiple architectural registers

A processor comprising:

• a decode unit to decode an instruction, the instruction to have a first register specifier to specify a base architectural register for a block of a number of sequential architectural registers that are to be used to perform the instruction;
• and
• an architectural register replacement unit coupled with the decode unit, the architectural register replacement unit to replace the base architectural register for the block with a replacement base architectural register, wherein a second register specifier for the replacement base architectural register is to be equal to one of:
• the first register specifier with its least significant single bit being binary zero, when the block includes only two sequential architectural registers;
• the first register specifier with its least significant two bits being binary zero, when the block includes one of only three and only four sequential architectural registers;
• the first register specifier with its least significant three bits being binary zero, when the block includes one of only five, only six, only seven, and only eight sequential architectural registers;
• and
• the first register specifier with its least significant four bits being binary zero, when the block includes one of only nine, only ten, only eleven, only twelve, only thirteen, only fourteen, and only fifteen sequential architectural registers.

A method performed by a processor, the method comprising:

• receiving an instruction, the instruction explicitly specifying a first architectural register and implicitly indicating at least a second architectural register, in which the second architectural register is implicitly for the instruction at a higher register number than the first architectural register;
• and
• replacing the first architectural register with a third architectural register at a lower register number than the first architectural register;
• and
• replacing the second architectural register with a fourth architectural register at a lower register number than the second architectural register.

A system to process instructions comprising:

• an interconnect;
• a processor coupled with the interconnect, the processor to receive an instruction that is to explicitly specify a first architectural register and to implicitly indicate at least a second architectural register, in which the second architectural register is implicitly for the instruction to be at a higher register number than the first architectural register, the processor to replace the first architectural register with a third architectural register, and to replace the second architectural register with a fourth architectural register, in which the third architectural register is to be at a lower register number than the first architectural register, and in which the fourth architectural register is to be at a lower register number than the second architectural register;
• and
• a dynamic random access memory (DRAM) coupled with the interconnect.