ISA extensions for synchronous coalesced accesses

A non-transitory computer readable medium having stored thereon a sequence of instructions which, when loaded and executed by a processor coupled to an apparatus causes the apparatus to:

• for an array of processors coupled to a memory, configure a head processor to set up a global map that corresponds data from certain ones of the processors contiguously to the memory, the head processor and the certain ones of the processors being in the array of processors;
• and
• configure the certain ones of the processors to block processor threads until respective times, derived from the global map, to access the memory;
• wherein the array of processors and the memory are part of a photonically-enabled synchronous coalesced access network (PSCAN);
• and at least one of the processors of the array access the memory through at least one shared photonic waveguide of the PSCAN;
• and
• the one or more of the processors of the array of processors perform one or more inflight data reorganizations based upon the at least one shared photonic waveguide accessed through the memory.

A multi-processing computer system comprising:

• an array of processors including:
• a head processor;
• and
• other processors;
• and
• a memory with computer code instructions stored thereon, the memory operatively coupled to the array of processors such that, when executed by the array of processors, the computer code instructions cause the system to:
• configure the head processor, by a setup instruction in an ISA (Instruction Set Architecture), to set up a global map that corresponds data from certain ones of the other processors in the array of processors contiguously to the memory;
• and
• configure the certain ones of the processors in the array by a blocking synchronous coalescing access (SCA) ISA instruction to block processor threads until respective times, derived from the global map, to access the memory;
• wherein the array of processors and the memory are part of a photonically-enabled synchronous coalesced access network (PSCAN);
• and
• one or more of the processors in the array of processors access the memory through at least one shared photonic waveguide of the PSCAN;
• and
• the one or more of the processors of the array of processors perform one or more inflight data reorganizations based upon the at least one shared photonic waveguide accessed through the memory.