Unified multiply unit
AssigneeImagination Technologies Limited
InventorLeonard Rarick
Life of this patent
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Abstract
Embodiments disclosed pertain to apparatuses, systems, and methods for performing multi-precision single instruction multiple data (SIMD) operations on integer, fixed point and floating point operands. Disclosed embodiments pertain to a circuit that is capable of performing concurrent multiply, fused multiply-add, rounding, saturation, and dot products on the above operand types. In addition, the circuit may facilitate 64-bit multiplication when Newton-Raphson, divide and square root operations are performed.
Claims20
A processor comprising a multiplication unit, the multiplication unit comprising:
- a modified booth encoder configured to:
- receive one or more multipliers and one or more multiplicands;
- for each of the one or more multiplicands, partition the bits in the multiplicand into overlapping groups of bits;
- and
- generate a plurality of partial products by determining a plurality of partial product rows, wherein each of the partial product rows corresponds to a partial product as a multiplication of one of the one or more multipliers with one of the groups of bits;
- a carry save adder comprising a plurality of first-level 5:3 compressors and a plurality of second-level 3:2 compressors, the carry save adder being configured to:
- receive the plurality of partial products generated by the modified booth encoder;
- and
- use the received partial products to obtain a first partial result and a second partial result;
- and
- an adder configured to:
- receive the first partial result and the second partial result;
- use the received first and second partial results to determine one or more output values;
- and
- output the one or more output values.
A non-transitory computer-readable medium comprising executable instructions to describe a processor comprising a multiplication unit, the multiplication unit comprising:
- a modified booth encoder configured to:
- receive one or more multipliers and one or more multiplicands;
- for each of the one or more multiplicands, partition the bits in the multiplicand into overlapping groups of bits;
- and
- generate a plurality of partial products by determining a plurality of partial product rows, wherein each of the partial product rows corresponds to a partial product as a multiplication of one of the one or more multipliers with one of the groups of bits;
- a carry save adder comprising a plurality of first-level 5:3 compressors and a plurality of second-level 3:2 compressors, the carry save adder being configured to:
- receive the plurality of partial products generated by the modified booth encoder;
- and
- use the received partial products to obtain a first partial result and a second partial result;
- and
- an adder configured to:
- receive the first partial result and the second partial result;
- use the received first and second partial results to determine one or more output values;
- and
- output the one or more output values.
A method of performing multiplication in a computer system, the method comprising:
- receiving one or more multipliers and one or more multiplicands at a modified booth encoder of the computer system;
- for each of the one or more multiplicands, partitioning the bits in the multiplicand into overlapping groups of bits;
- the modified booth encoder generating a plurality of partial products by determining a plurality of partial product rows, wherein each of the partial product rows corresponds to a partial product as a multiplication of one of the one or more multipliers with one of the groups of bits;
- using the plurality of partial products at a carry save adder of the computer system to obtain a first partial result and a second partial result, the carry save adder comprising a plurality of first-level 5:3 compressors and a plurality of second-level 3:2 compressors;
- using the first and second partial results at an adder of the computer system to determine one or more output values;
- and
- outputting the one or more output values.
Dependencies are inferred from the claim text.