Disaggregated memory appliance having a management processor that accepts request from a plurality of hosts for management, configuration and provisioning of memory
AssigneeSamsung Electronics Co., Ltd.
InventorsSteven L. Shrader, Harry R. Rogers, Robert Brennan, Ian P. Shaeffer
Life of this patent
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Abstract
Example embodiments provide a disaggregated memory appliance, comprising: a plurality of leaf memory switches that manage one or more memory channels of one or more of leaf memory modules; a low-latency memory switch that arbitrarily connects one or more external processors to the plurality of leaf memory modules over a host link; and a management processor that responds to requests from one or more external processors for management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance.
Claims13
A memory appliance, comprising:
- a plurality of leaf memory switches that each manage one or more memory channels of one or more of leaf memory modules;
- a low-latency memory switch that arbitrarily connects one or more external processors to the plurality of leaf memory modules over a host link;
- and
- a management processor that responds to requests from one or more external processors for management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance but does not participate in movement of data except to access resources provisioned for the management processor;
- wherein the management processor is implemented as part of a compute complex that enables multiple functions, including boot and initial configuration of the memory appliance, coordination of memory allocation for the one or more external processors, compute offloading, and setup of wormhole switching in which endpoints use target routing data supplied during a memory provisioning process to effect low-latency switching of memory data flits and metadata.
A method for providing a disaggregated memory appliance, comprising:
- coupling a low-latency memory switch to a host link over which the low-latency memory switch receives requests and traffic from one or more external processors;
- using a plurality of leaf links to connect the low-latency memory switch to a plurality of leaf memory switches that are connected to, and manage, one or more memory channels of one or more of leaf memory modules;
- and
- responding, by a management processor, to the requests from the one or more external processors for management, maintenance, configuration and provisioning of the leaf memory modules within the memory appliance but not participating in movement of data except to access resources provisioned for the management processor;
- wherein the management processor is implemented as part of a compute complex that enables multiple functions, including boot and initial configuration of the memory appliance, coordination of memory allocation for the one or more external processors, compute offloading, and setup of wormhole switching in which endpoints use target routing data supplied during a memory provisioning process to effect low-latency switching of memory data flits and metadata.
Dependencies are inferred from the claim text.