System and methodology for low latency error management within a shared non-volatile memory architecture
AssigneeWestern Digital Technologies, Inc.
InventorsLuiz M. Franca-Neto, Robert Eugeniu Mateescu
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Abstract
Various aspects directed towards facilitating error management within a shared non-volatile memory (NVM) architecture are disclosed. Data is stored in an NVM array, and error correction vector (ECV) information associated with the NVM array is stored in a content addressable memory (CAM). A parallel query of the NVM array and the CAM is then performed, which includes a query of the NVM array that yields a readout of the NVM array, and a query of the CAM that yields an ECV corresponding to the readout of the NVM array.
Claims20
A method, comprising:
- employing a processor to execute computer executable instructions stored on a computer readable storage medium to implement the following acts:
- storing data in a non-volatile memory (NVM) array;
- storing error correction vector (ECV) information associated with the NVM array in a content addressable memory (CAM);
- and
- performing a parallel query of the NVM array and the CAM, wherein the parallel query includes a query of the NVM array that yields a readout of the NVM array and a query of the CAM that yields an ECV corresponding to the readout of the NVM array and wherein the parallel query causes latencies from the readout of the NVM array and latencies associated with a construction of the ECV corresponding to the readout of the NVM array to occur in parallel.
A system comprising:
- a processing unit comprising at least one processor;
- a non-volatile memory (NVM) controlled by the processing unit, the NVM configured to store data in an NVM array;
- a content addressable memory (CAM) controlled by the processing unit, the CAM configured to store error correction vector (ECV) information associated with the NVM array;
- and
- a query component controlled by the processing unit, the query component configured to perform a parallel query of the NVM array and the CAM, wherein the parallel query includes a query of the NVM array that yields a readout of the NVM array and a query of the CAM that yields an ECV corresponding to the readout of the NVM array, and wherein the parallel query causes latencies from the readout of the NVM array and latencies associated with a construction of the ECV corresponding to the readout of the NVM array to occur in parallel.
An apparatus, comprising:
- means for storing data in a non-volatile memory (NVM) array;
- means for storing error correction vector (ECV) information associated with the NVM array in a content addressable memory (CAM);
- and
- means for performing a parallel query of the NVM array and the CAM, wherein the parallel query includes a query of the NVM array that yields a readout of the NVM array and a query of the CAM that yields an ECV corresponding to the readout of the NVM array, and wherein the parallel query causes latencies from the readout of the NVM array and latencies associated with a construction of the ECV corresponding to the readout of the NVM array to occur in parallel.
Dependencies are inferred from the claim text.