Back to results
US 10,254,977 B2Granted
Achieving consistent read times in multi-level non-volatile memory
AssigneeIntel Corporation
InventorsAnand S. Ramalingam, Pranav Kalavade
Life of this patent
Estimating the term…
Abstract
Systems, apparatuses and methods may provide for technology that reads a lower page, one or more intermediate pages and a last page from a set of multi-level non-volatile memory (NVM) cells, wherein one or more of a lower read time associated with the lower page or a last read time associated with the last page is substantially similar to an intermediate read time associated with the one or more intermediate pages.
Claims25
A system comprising:
- a device controller apparatus including a transfer buffer;
- and
- a non-volatile memory (NVM) communicatively coupled to the device controller apparatus, the NVM including:
- a set of multi-level NVM cells, wherein each of the multi-level NVM cells includes at least four bits;
- and
- a chip controller apparatus that includes one or more substrates and logic, implemented in fixed-functionality hardware and coupled to the one or more substrates, the logic to program the set of multi-level NVM cells and read one or more pages from the set of multi-level NVM cells.
3 more elements
An apparatus comprising:
- one or more substrates;
- and
- logic, implemented in fixed-functionality hardware and coupled to the one or more substrates, the logic to:
- read one or more pages from a set of multi-level non-volatile memory (NVM) cells, wherein each of the multi-level NVM cells includes at least four bits, and
- program the multi-level NVM cells.
2 more elements
A method comprising:
- reading, by logic implemented in fixed-functionality hardware, one or more pages from a set of multi-level non-volatile memory (NVM) cells, wherein each of the multi-level NVM cells includes at least four bits;
- and
- programming, with the logic, the multi-level NVM cells.
Dependencies are inferred from the claim text.