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US 10,254,976 B2Granted
Methods and systems for using state vector data in a state machine engine
AssigneeMicron Technology, Inc.
InventorsDavid R. Brown, Harold B Noyes
Life of this patent
Estimating the term…
Abstract
A state machine engine includes a state vector system. The state vector system includes an input buffer configured to receive state vector data from a restore buffer and to provide state vector data to a state machine lattice. The state vector system also includes an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to a save buffer.
Claims21
A system, comprising
- a host device comprising a processor and a memory coupled to the processor;
- and
- a state machine engine coupled to the host device via a bus interface, wherein the state machine engine comprises:
- a state machine lattice;
- a restore buffer configured to receive state vector data from the host via the bus interface coupling the host to the state machine engine;
- a save buffer configured to provide state vector data to the host via the bus interface coupling the host to the state machine engine;
- and
- a state vector system coupled to the state machine lattice, wherein the state vector system comprises:
- an input buffer configured to receive state vector data from the restore buffer of the state machine engine and to provide state vector data to the state machine lattice to initialize or restore a state of the state machine lattice, wherein the state vector data includes a state vector as an indication of a state of all or certain configurable elements of the state machine lattice at a given moment as an indication of a particular state of the state machine lattice;
- and
- an output buffer configured to receive state vector data from the state machine lattice and to provide state vector data to the save buffer of the state machine engine as save map data.
8 more elements
A state machine engine, comprising:
- a restore buffer configured to receive state vector data from a host external to the state machine engine via a bus interface coupling the host to the state machine engine;
- a save buffer configured to provide state vector data to the host via the bus interface coupling the host to the state machine engine;
- and
- a state vector system configured to store a plurality of state vectors of a state machine lattice as state vector data as indications of states of all or certain configurable elements of the state machine lattice at a given moment during an analysis of data by the state machine lattice and to provide a state vector to the state machine lattice to restore the state machine lattice to a particular state corresponding to the provided state vector for further analysis of the data by the state machine lattice.
1 more element
A system, comprising:
- a state machine engine, comprising:
- an intra-rank (IR) bus and process buffer interface configured to facilitate the analyzing of multiple data sets in parallel through a logical rank of state machine lattices;
- and
- a state vector system coupled to the IR bus and process buffer interface, the state vector system comprising:
- an input buffer configured to receive state vector data from a first state machine lattice via the IR bus and process buffer interface and to provide the state vector data to a second state machine lattice, wherein the state vector data includes a state vector as an indication of a state of all or certain configurable elements of the first state machine lattice at a given moment as an indication of a particular state of the first state machine lattice;
- and
- an output buffer configured to receive second state vector data from the second state machine lattice and to provide the second state vector data to the first state machine lattice via the IR bus and process buffer interface.
4 more elements
A device, comprising:
- a state machine lattice configured to generate state vector data, wherein the state vector data includes a state vector as an indication of a state of all or certain configurable elements of the state machine lattice at a given moment as an indication of a particular state of the state machine lattice;
- a cache configured to store second state vector data;
- a buffer coupled to the state machine lattice and the cache and configured to receive the state vector data from the state machine lattice and the second state vector data from the cache;
- and
- an intra-rank (IR) bus and process buffer interface configured to facilitate the analyzing of multiple data sets in parallel through a logical rank of state machine lattices, wherein the IR bus and process buffer interface is coupled to the buffer, wherein the buffer is configured to provide the state vector data and the second state vector data to the intra-rank (IR) bus and process buffer interface.
2 more elements
Dependencies are inferred from the claim text.