Power management using duty cycles

An integrated circuit comprising:

• a first global power rail configured to be held at a first global voltage;
• a second global power rail configured to be held at a second global voltage;
• a global clock tree configured to propagate a global clock signal;
• and
• multiple power domains, each power domain including:
• a local power rail configured to be held at a local voltage;
• a local clock tree configured to propagate a local clock signal;
• a circuit load coupled to the local power rail and the local clock tree, the circuit load configured to operate using the local voltage and the local clock signal;
• and
• power state control means for adjusting a power state of the circuit load in accordance with a duty cycle corresponding to a timeslot that is separated into multiple time periods, the power state control means configured to couple at least the first global power rail or the second global power rail to the local power rail and the global clock tree to the local clock tree.

A method for power management using duty cycles, the method comprising:

• distributing multiple global voltages to each of multiple power domains of an integrated circuit via multiple global power rails;
• propagating a global clock signal to each of the multiple power domains of the integrated circuit via a global clock tree;
• and
• controlling power states in the multiple power domains by, for each respective power domain having a circuit load:
• distributing a local voltage to the circuit load of the respective power domain via a local power rail;
• propagating a local clock signal to the circuit load of the respective power domain via a local clock tree;
• and
• adjusting the local voltage and the local clock signal using the multiple global voltages and the global clock signal in accordance with a duty cycle corresponding to a timeslot including multiple time periods per timeslot, each respective time period corresponding to a respective power state having a voltage frequency setting.

An integrated circuit comprising:

• a first global power rail configured to be held at a first global voltage;
• a second global power rail configured to be held at a second global voltage;
• a global clock tree configured to propagate a global clock signal;
• and
• multiple power domains, each power domain including:
• a local power rail configured to be held at a local voltage;
• a local clock tree configured to propagate a local clock signal;
• and
• power state control circuitry configured to implement a finite state machine, the finite state machine including:
• a first power state corresponding to the local power rail being coupled to the first global power rail and the local clock signal being a function of the global clock signal and a first divisor value;
• and
• a second power state corresponding to the local power rail being coupled to the second global power rail and the local clock signal being a function of the global clock signal and a second divisor value,
• wherein the finite state machine is configured to trigger a state transition based on at least one timer derived from a duty cycle.