Method of operating semiconductor device
AssigneeSamsung Electronics Co., Ltd.
InventorsHyo-Sang Jung, Sang-Wook Ju, Jung-Hun Heo
Life of this patent
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Abstract
Systems, apparatuses, and methods of power management for a system on a chip (SoC) are described. In one method, the operational states of the cores/processors of the SoC are monitored and, if a core/processor is in idle or standby mode, the rate of the clock signal driving a component, such as a memory interface, associated with the idle core/processor is reduced, thereby reducing power consumption.
Claims16
A method of operating a system on a chip (SoC), comprising:
- providing a first internal (INT) clock signal with a first clock rate to each intellectual property (IP) on the SoC;
- examining states of a first core/processor and a second core/processor provided on the SoC;
- if both the first core/processor and the second core/processor are in an idle state, changing the first INT clock signal to a second INT clock signal having a second clock rate different from the first clock rate;
- providing a memory interface (MIF) clock signal with a third clock rate to one or more memory interfaces on the SoC;
- and
- when both the first core/processor and the second core/processor are in the idle state, changing the MIF clock signal to a fourth clock rate different from the third clock rate.
A method of operating a system on a chip (SoC), comprising:
- providing a first internal (INT) clock signal at a first clock rate to a first intellectual property (IP) on the SoC;
- providing a second internal (INT) clock signal at a second clock rate to a second IP on the SoC;
- and
- if both of a first core/processor and a second core/processor provided on the SoC are in an idle state, changing the first INT clock signal to the first IP to a third clock rate and changing the second INT clock signal to the second IP to a fourth clock rate,
- wherein the third and fourth clock rates are different.
A system on a chip (SoC), comprising:
- one or more cores/processors;
- one or more intellectual properties (IPs) controlled by the one or more cores/processors;
- an internal (INT) clock module which receives a reference clock signal which drives one or more components on the SoC and generates, from the reference clock signal, one or more INT clock signals which drive the one or more IPs, where a clock rate of each of the one or more INT clock signals is based on an operational state of at least one corp/processor which controls the IP receiving the INT clock signal;
- one or more memory interfaces;
- and
- a memory interface (MIF) clock module which receives the reference clock signal and generates, from the reference clock signal, one or more MIF clock signals which drive the one or more memory interfaces, where a clock rate of each of the one or more MIF clock signals is based on an operational state of any cores/processors associated with the memory interface receiving the MIF clock signal.
A method of power management for a system on a chip (SoC) which comprises one or more cores/processors and one or more intellectual properties (IPs), comprising:
- monitoring an operational state of the one or more cores/processors;
- setting a clock rate of an internal clock (INT) signal driving at least one of the one or more IPs based on an operational state of a core/processor of the one or more cores/processors, wherein the core/processor controls the at least one IP, and wherein the INT clock signal is generated from a reference signal which drives one or more components of the SoC;
- and
- setting a clock rate of a memory interface (MIF) clock signal driving at least one memory interface included on the SoC, wherein the clock rate is based on an operational state of a core/processor of the one or more cores/processors, wherein the core/processor is associated with the at least one memory interface, and wherein the MIF clock signal is generated from the reference signal which drives one or more components of the SoC.
Dependencies are inferred from the claim text.