Low inrush circuit for power up and deep power down exit

A system comprising:

• a processor;
• a low energy integrated circuit;
• a memory controller coupled to the processor and the low energy integrated circuit;
• and
• an inrush circuit coupled to the low energy integrated circuit, the inrush circuit comprising:
• a regulator comprising at least one driver device configured to generate a first current associated with a load comprising the low energy integrated circuit;
• a bias generator configured to generate a second current to charge a load capacitor coupled with a power terminal of the low energy integrated circuit;
• and
• an enable circuit configured to enable the bias generator and disable the regulator responsive to a load voltage being below a threshold voltage, and further configured to enable the regulator to generate the first current and disable the bias generator responsive to the load voltage being above the threshold voltage.

A method comprising:

• receiving an input identifying a transition of an operational mode of a low energy integrated circuit from a first operational mode to a second operational mode;
• enabling a bias generator, using an enable circuit comprising at least a flipflop and an inverter, in response to receiving the input, the bias generator generating a bias current provided to a load capacitor at a power terminal of the low energy integrated circuit;
• charging the load capacitor based on the bias current;
• and
• enabling a regulator, using the enable circuit, in response to the load capacitor being charged to a designated threshold, the enabling of the regulator generating;
• using at least one driver device, an operational current provided to the low energy integrated circuit.