US 10,254,811 B2 · On-chip power sequence validator and monitor

Abstract

Systems, apparatuses, and methods for monitoring power rails during power sequences are disclosed. An apparatus includes one or more voltage regulators, a plurality of registers, and control logic. The control logic is configured to monitor a power rail generated by a voltage regulator. The control logic generates and stores an indication of pass or failure in a first register for the power rail during a power sequence. The control logic enables the first register to be read by an external device subsequent to completion of the power sequence. In another embodiment, the control logic generates a pass indicator if the power rail is less than a first voltage value on a first boundary of a timing interval and if the power rail is greater than a second voltage value on a second boundary of the timing interval. Otherwise, a fail indicator is generated.

Claims20

Dependent claims

A system comprising:

processing logic;
a plurality of registers;
and
control logic configured to:
monitor a power rail generated by a voltage regulator, wherein the power rail provides power to at least a portion of the processing logic;
determine whether a voltage transition occurs during a given time window, wherein the given time window is bounded by first and second time boundaries;
generate a pass indication and a fail indication for the power rail during a power sequence responsive to determining the voltage transition occurs but outside of the given time window;
and
provide the pass indication and the fail indication to an external entity subsequent to completion of the power sequence.

6 more elements

Dependencies are inferred from the claim text.

On-chip power sequence validator and monitor

Life of this patent

On-chip power sequence validator and monitor

Life of this patent

Abstract

Claims20