Regulator circuit with enhanced ripple reduction speed

A regulator circuit comprising:

• an operational amplifier (OP-amp) configured to drive a first node as a first voltage signal by amplifying a difference between an input voltage signal and a feedback voltage signal, wherein an output resistance of the OP-amp is controlled based on a first bias current;
• a buffer configured to drive a second node as a second voltage signal generated based on the first voltage signal, wherein an output resistance of the buffer is controlled based on a second bias current;
• a power transistor including a drain terminal receiving a supply voltage, a gate terminal connected to the second node, and a source terminal connected to a third node;
• a sense transistor including a drain terminal connected to a fourth node, a gate terminal connected to the second node, and a source terminal connected to the third node;
• a voltage divider configured to generate the feedback voltage signal by dividing an output voltage signal of the third node;
• a load including a terminal connected to the third node and another terminal receiving a ground voltage;
• a feedback current generator configured to provide first through third feedback currents corresponding to a ripple of the output voltage signal to the first through third nodes respectively to enhance a speed at which the ripple in the output voltage signal is reduced;
• and
• a dynamic bias current controller configured to increase stability of the regulator circuit and minimize a quiescent current by agile control of the first and second bias currents in response to a sense current flowing from a supply voltage node to the drain terminal of the sense transistor through the fourth node.

A regulator circuit comprising:

• an operational amplifier configured to drive a first node as a first voltage signal generated by amplifying a difference between an input voltage signal and a feedback voltage signal, wherein the feedback voltage signal corresponds to an output voltage signal;
• a buffer configured to drive a second node as a second voltage signal generated based on the first voltage signal;
• a power transistor connected between a supply voltage and a third node, and gated to receive the second voltage signal, wherein the output voltage signal is generated at the third node;
• and
• a feedback current generator connected to the third node and receiving the output voltage signal, and configured to provide first, second and third feedback currents to the first, second and third nodes, respectively, wherein the first, second and third feedback currents enhance a speed at which a ripple in the output voltage signal is reduced.