US 10,254,610 B2Granted

3T pixel structure and related liquid crystal display

AssigneeShenzhen China Star Optoelectronics Technology Co., Ltd.

InventorXiangwei Jiang

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Abstract

A 3T pixel structure is provided. The 3T pixel structure includes: a substrate, on which a lower common electrode and a scan line are positioned; a first dielectric layer, positioned on the lower common electrode, the scan line and the substrate; a charge-sharing thin film transistor (TFT), including a source, a drain, and a gate, the source and the drain of the charge-sharing TFT being positioned on the first dielectric layer; a data line, positioned on the first dielectric layer; a second dielectric layer, positioned on the source, the drain, the data line of the charge-sharing TFT and the first dielectric layer; and an upper common electrode, positioned on the second dielectric layer. The second dielectric layer has a source hole to allow the upper common electric layer to contact the first source and electrically connect to the first source through the source hole.

Claims13

Dependent claims

A 3T pixel structure, comprising:

a substrate, on which a lower common electrode and a scan line are positioned;
a first dielectric layer, positioned on the lower common electrode, the scan line and the substrate;
a charge-sharing thin film transistor (TFT), comprising a source, a drain, and a gate, the source and the drain of the charge-sharing TFT being positioned on the first dielectric layer;
a data line, positioned on the first dielectric layer;
a second dielectric layer, positioned on the source, the drain, the data line of the charge-sharing TFT and the first dielectric layer;
and
an upper common electrode, positioned on the second dielectric layer;
wherein the second dielectric layer has a source hole to allow the upper common electric layer to contact the first source and electrically connect to the first source through the source hole;
further comprising a third dielectric layer, positioned on the upper common electrode and the second dielectric layer;
and a pixel electrode layer, positioned on the third dielectric layer;
a main pixel TFT, comprising a source, a drain, and a gate, the source, the drain, and the gate of the main pixel TFT being positioned on the first dielectric layer;
and a sub-pixel TFT, comprising a source, a drain, and a gate, the source, the drain, and the gate of the sub-pixel TFT being positioned on the first dielectric layer,
wherein the gate of the charge-sharing TFT is positioned on the second dielectric layer;
and
wherein the source of the main pixel TFT is electrically connected to the drain of the sub-pixel TFT, the source of the sub-pixel TFT is electrically connected to the drain of the charge-sharing TFT, the gates of the main pixel TFT, the sub-pixel TFT, and the charge-sharing TFT are all electrically connected to the scan line.

12 more elements

A 3T pixel structure, comprising:

a substrate, on which a lower common electrode and a scan line are positioned;
a first dielectric layer, positioned on the lower common electrode, the scan line and the substrate;
a charge-sharing thin film transistor (TFT), comprising a source, a drain, and a gate, the source and the drain of the charge-sharing TFT being positioned on the first dielectric layer;
a data line, positioned on the first dielectric layer;
a second dielectric layer, positioned on the source, the drain, the data line of the charge-sharing TFT and the first dielectric layer;
an upper common electrode, positioned on the second dielectric layer, wherein the second dielectric layer has a source hole to allow the upper common electric layer to contact the first source and electrically connect to the first source through the source hole;
a third dielectric layer, positioned on the upper common electrode and the second dielectric layer;
a pixel electrode layer, positioned on the third dielectric layer;
a main pixel TFT, comprising a source, a drain, and a gate, the source, the drain, and the gate of the main pixel TFT being positioned on the first dielectric layer;
a sub-pixel TFT, comprising a source, a drain, and a gate, the source, the drain, and the gate of the sub-pixel TFT being positioned on the first dielectric layer, wherein the gate of the charge-sharing TFT is positioned on the second dielectric layer, the source of the main pixel TFT is electrically connected to the drain of the sub-pixel TFT, the source of the sub-pixel TFT is electrically connected to the drain of the charge-sharing TFT, the gates of the main pixel TFT, the sub-pixel TFT, and the charge-sharing TFT are all electrically connected to the scan line;
a first capacitor, formed by a first plate positioned on the first dielectric layer and a portion of the lower common electrode corresponding to the first plate;
and
a second capacitor, formed by formed by a second plate positioned on the first dielectric layer and a portion of the lower common electrode corresponding to the second plate, wherein the first plate is electrically connected to the drain of the main pixel TFT, and the second plate is electrically connected to the source of the sub-pixel TFT and the drain of the charge-sharing TFT;
wherein the source of the sub-pixel TFT contacts and electrically connects to the drain of the charge-sharing TFT, and a common node of the source of the sub-pixel TFT and the drain of the charge-sharing TFT is electrically connected to the second plate.

11 more elements

A liquid crystal display, comprising a 3T pixel structure, the 3T pixel structure comprising:

a substrate, on which a lower common electrode and a scan line are positioned;
a first dielectric layer, positioned on the lower common electrode, the scan line and the substrate;
a charge-sharing thin film transistor (TFT), comprising a source, a drain, and a gate, the source and the drain of the charge-sharing TFT being positioned on the first dielectric layer;
a data line, positioned on the first dielectric layer;
a second dielectric layer, positioned on the source, the drain, the data line of the charge-sharing TFT and the first dielectric layer;
and
an upper common electrode, positioned on the second dielectric layer;
wherein the second dielectric layer has a source hole to allow the upper common electric layer to contact the first source and electrically connect to the first source through the source hole;
the 3T pixel structure further comprises a third dielectric layer, positioned on the upper common electrode and the second dielectric layer;
and a pixel electrode layer, positioned on the third dielectric layer;
wherein the 3T pixel structure further comprises:
a main pixel TFT, comprising a source, a drain, and a gate, the source, the drain, and the gate of the main pixel TFT being positioned on the first dielectric layer;
and
a sub-pixel TFT, comprising a source, a drain, and a gate, the source, the drain, and the gate of the sub-pixel TFT being positioned on the first dielectric layer,
wherein the gate of the charge-sharing TFT is positioned on the second dielectric layer;
and
wherein the source of the main pixel TFT is electrically connected to the drain of the sub-pixel TFT, the source of the sub-pixel TFT is electrically connected to the drain of the charge-sharing TFT, the gates of the main pixel TFT, the sub-pixel TFT, and the charge-sharing TFT are all electrically connected to the scan line.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/121,927Filed 16 Jun 2016
Priority: CN 2016 1 033927420 May 2016
Published: US 2018/0149939 A131 May 2018
Granted: 9 Apr 2019
Term ends: Not estimatedThe source records don’t support an estimate.

Classification15 codes

G02F 1/136286
Active matrix addressed cells: wiring, e.g. gate line, drain line
G02F 1/134336
Characterised by their geometrical arrangement: matrix
G02F 1/136227
Active matrix addressed cells: through-hole connection of the pixel electrode to the active element through an insulation layer
G02F 1/13624
Active matrix addressed cells: having more than one switching element per pixel