Array substrate including pixel electrode and drain electrode in direct contact to each other, and method of manufacturing the same, display panel, and display device

A method of manufacturing an array substrate comprising a plurality of pixel regions, comprising:

• providing a base substrate;
• forming a thin film transistor and a pixel electrode in each of the pixel regions;
• forming an insulating layer between a drain electrode of the thin film transistor and the pixel electrode;
• forming the gate insulating layer and an active layer of the thin film transistor by one patterning process,
• wherein the forming an insulating layer comprises:
• forming in the insulating layer a via-hole through which the drain electrode is in direct electrical contact with the pixel electrode,
• wherein the insulating layer is a gate insulating layer,
• wherein the forming the gate insulating layer and an active layer of the thin film transistor by one patterning process further comprises:
• forming a gate insulating layer and a semiconductor layer successively;
• coating photoresist onto the semiconductor layer, exposing the photoresist using a grey tone mask plate or a halftone mask plate to form a photoresist fully-reserved region, a photoresist partially-reserved region and a photoresist fully-unreserved region, the photoresist fully-reserved region corresponds to a region of the active layer, the photoresist fully-unreserved region corresponds to a region of the via-hole, and the photoresist partially-reserved region corresponds to other regions;
• removing the semiconductor layer and the insulating layer at the photoresist fully-unreserved region to form the via-hole;
• removing the photoresist at the photoresist partially-reserved region through an ashing process;
• removing the semiconductor layer at the photoresist partially-reserved region;
• and
• peeling off a remaining part of the photoresist to form the active layer of the thin film transistor.

A method of manufacturing an array substrate comprising a plurality of pixel regions, comprising:

• providing a base substrate;
• forming a thin film transistor and a pixel electrode in each of the pixel regions;
• forming an insulating layer between a drain electrode of the thin film transistor and the pixel electrode;
• forming the gate insulating layer and a gate electrode of the thin film transistor by one patterning process;
• wherein the forming an insulating layer comprises:
• forming in the insulating layer a via-hole through which the drain electrode is in direct electrical contact with the pixel electrode,
• wherein the insulating layer is a gate insulating layer,
• wherein the thin film transistor is a top-gate thin film transistor, and the method further comprises:
• providing a base substrate;
• forming a source electrode and the drain electrode of the thin film transistor on the base substrate;
• forming an active layer, two ends of which are directly overlapped onto the source electrode and the drain electrode respectively;
• forming the gate insulating layer covering the active layer, the source electrode and the drain electrode;
• forming a gate metal layer on the gate insulating layer, performing a patterning process to the gate insulating layer and the gate metal layer to form the gate electrode of the thin film transistor, and forming the via-hole in the gate insulating layer to expose a part of the drain electrode;
• forming a plate-like pixel electrode on the gate insulating layer, wherein a part of the pixel electrode is inserted into the via-hole to be in direct electrical contact with the drain electrode;
• forming a passivation layer covering the pixel electrode and the pixel electrode;
• and
• forming a slit common electrode on the passivation layer.