Display device

A semiconductor device comprising:

• a pixel portion comprising:
• a pixel transistor;
• and
• a capacitor comprising a first electrode and a second electrode;
• a first protective circuit comprising:
• a first non-linear element comprising a first oxide semiconductor layer;
• a second non-linear element comprising a second oxide semiconductor layer;
• and
• a third non-linear element comprising a third oxide semiconductor layer;
• and
• a second protective circuit comprising:
• a fourth non-linear element comprising a fourth oxide semiconductor layer;
• a fifth non-linear element comprising a fifth oxide semiconductor layer;
• and
• a sixth non-linear element comprising a sixth oxide semiconductor layer,
• wherein the first protective circuit is electrically connected to the second protective circuit,
• wherein a first conductive layer comprises:
• a gate electrode of the first non-linear element;
• and
• a first wiring,
• wherein a second conductive layer comprises a gate electrode of the second non-linear element,
• wherein a third conductive layer comprises a gate electrode of the third non-linear element,
• wherein a fourth conductive layer comprises one of a source electrode and a drain electrode of the first non-linear element, and comprises one of a source electrode and a drain electrode of the third non-linear element,
• wherein a fifth conductive layer comprises:
• one of a source electrode and a drain electrode of the second non-linear element;
• the other of the source electrode and the drain electrode of the third non-linear element;
• and
• a second wiring,
• wherein a sixth conductive layer comprises the other of the source electrode and the drain electrode of the first non-linear element, and comprises the other of the source electrode and the drain electrode of the second non-linear element,
• wherein a seventh conductive layer comprises:
• a gate electrode of the fourth non-linear element;
• and
• a third wiring electrically connected to the second electrode of the capacitor,
• wherein an eighth conductive layer comprises a gate electrode of the fifth non-linear element,
• wherein a ninth conductive layer comprises a gate electrode of the sixth non-linear element,
• wherein a tenth conductive layer comprises one of a source electrode and a drain electrode of the fourth non-linear element, and comprises one of a source electrode and a drain electrode of the sixth non-linear element,
• wherein an eleventh conductive layer comprises:
• one of a source electrode and a drain electrode of the fifth non-linear element;
• and
• the other of the source electrode and the drain electrode of the sixth non-linear element,
• wherein a twelfth conductive layer comprises the other of the source electrode and the drain electrode of the fourth non-linear element, and comprises the other of the source electrode and the drain electrode of the fifth non-linear element,
• wherein the fourth conductive layer is in direct contact with the first conductive layer,
• wherein the fifth conductive layer is in direct contact with the second conductive layer,
• wherein the sixth conductive layer is in direct contact with the third conductive layer,
• wherein the tenth conductive layer is in direct contact with the seventh conductive layer,
• wherein the eleventh conductive layer is in direct contact with the eighth conductive layer,
• wherein the twelfth conductive layer is in direct contact with the ninth conductive layer,
• wherein the first conductive layer is electrically connected to each of the first oxide semiconductor layer and the third oxide semiconductor layer, via the fourth conductive layer,
• wherein the second conductive layer is electrically connected to each of the second oxide semiconductor layer and the third oxide semiconductor layer, via the fifth conductive layer,
• wherein the third conductive layer is electrically connected to each of the first oxide semiconductor layer and the second oxide semiconductor layer, via the sixth conductive layer,
• wherein the seventh conductive layer is electrically connected to each of the fourth oxide semiconductor layer and the sixth oxide semiconductor layer, via the tenth conductive layer,
• wherein the eighth conductive layer is electrically connected to each of the fifth oxide semiconductor layer and the sixth oxide semiconductor layer, via the eleventh conductive layer,
• wherein the ninth conductive layer is electrically connected to each of the fourth oxide semiconductor layer and the fifth oxide semiconductor layer, via the twelfth conductive layer,
• wherein one of a source electrode and a drain electrode of the pixel transistor is electrically connected to the first electrode of the capacitor,
• wherein third wiring is electrically connected to the second electrode of the capacitor,
• wherein one of a source electrode and a drain electrode of the pixel transistor is electrically connected to the first electrode of the capacitor, and
• wherein one of the first wiring and the second wiring is electrically connected to the other of a source electrode and the drain electrode of the pixel transistor.